[PATCH] Hexagon (target/hexagon) Add overrides for count trailing zeros/ones

[PATCH] Hexagon (target/hexagon) Add overrides for count trailing zeros/ones

[Taylor Simpson]

The following instructions are overriden
    S2_ct0            Count trailing zeros
    S2_ct1            Count trailing ones
    S2_ct0p           Count trailing zeros (register pair)
    S2_ct1p           Count trailing ones (register pair)

These instructions are not handled by idef-parser because the
imported semantics uses bit-reverse.  However, they are
straightforward to implement in TCG with tcg_gen_ctzi_*

Test cases added to tests/tcg/hexagon/misc.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
 target/hexagon/gen_tcg.h | 24 +++++++++++++++++
 tests/tcg/hexagon/misc.c | 56 +++++++++++++++++++++++++++++++++++++++-
 2 files changed, 79 insertions(+), 1 deletion(-)

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index bcf0cf466a..45f92adf6c 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -1058,6 +1058,30 @@
 #define fGEN_TCG_SL2_jumpr31_fnew(SHORTCODE) \
     gen_cond_jumpr31(ctx, TCG_COND_NE, hex_new_pred_value[0])
 
+/* Count trailing zeros/ones */
+#define fGEN_TCG_S2_ct0(SHORTCODE) \
+    do { \
+        tcg_gen_ctzi_tl(RdV, RsV, 32); \
+    } while (0)
+#define fGEN_TCG_S2_ct1(SHORTCODE) \
+    do { \
+        tcg_gen_not_tl(RdV, RsV); \
+        tcg_gen_ctzi_tl(RdV, RdV, 32); \
+    } while (0)
+#define fGEN_TCG_S2_ct0p(SHORTCODE) \
+    do { \
+        TCGv_i64 tmp = tcg_temp_new_i64(); \
+        tcg_gen_ctzi_i64(tmp, RssV, 64); \
+        tcg_gen_extrl_i64_i32(RdV, tmp); \
+    } while (0)
+#define fGEN_TCG_S2_ct1p(SHORTCODE) \
+    do { \
+        TCGv_i64 tmp = tcg_temp_new_i64(); \
+        tcg_gen_not_i64(tmp, RssV); \
+        tcg_gen_ctzi_i64(tmp, tmp, 64); \
+        tcg_gen_extrl_i64_i32(RdV, tmp); \
+    } while (0)
+
 /* Floating point */
 #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
     gen_helper_conv_sf2df(RddV, cpu_env, RsV)
diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c
index e73ab57334..e126751e3a 100644
--- a/tests/tcg/hexagon/misc.c
+++ b/tests/tcg/hexagon/misc.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -21,6 +21,7 @@
 typedef unsigned char uint8_t;
 typedef unsigned short uint16_t;
 typedef unsigned int uint32_t;
+typedef unsigned long long uint64_t;
 
 
 static inline void S4_storerhnew_rr(void *p, int index, uint16_t v)
@@ -333,6 +334,57 @@ void test_l2fetch(void)
                   "l2fetch(r0, r3:2)\n\t");
 }
 
+static inline int ct0(uint32_t x)
+{
+    int res;
+    asm("%0 = ct0(%1)\n\t" : "=r"(res) : "r"(x));
+    return res;
+}
+
+static inline int ct1(uint32_t x)
+{
+    int res;
+    asm("%0 = ct1(%1)\n\t" : "=r"(res) : "r"(x));
+    return res;
+}
+
+static inline int ct0p(uint64_t x)
+{
+    int res;
+    asm("%0 = ct0(%1)\n\t" : "=r"(res) : "r"(x));
+    return res;
+}
+
+static inline int ct1p(uint64_t x)
+{
+    int res;
+    asm("%0 = ct1(%1)\n\t" : "=r"(res) : "r"(x));
+    return res;
+}
+
+void test_count_trailing_zeros_ones(void)
+{
+    check(ct0(0x0000000f), 0);
+    check(ct0(0x00000000), 32);
+    check(ct0(0x000000f0), 4);
+
+    check(ct1(0x000000f0), 0);
+    check(ct1(0x0000000f), 4);
+    check(ct1(0x00000000), 0);
+    check(ct1(0xffffffff), 32);
+
+    check(ct0p(0x000000000000000fULL), 0);
+    check(ct0p(0x0000000000000000ULL), 64);
+    check(ct0p(0x00000000000000f0ULL), 4);
+
+    check(ct1p(0x00000000000000f0ULL), 0);
+    check(ct1p(0x000000000000000fULL), 4);
+    check(ct1p(0x0000000000000000ULL), 0);
+    check(ct1p(0xffffffffffffffffULL), 64);
+    check(ct1p(0xffffffffff0fffffULL), 20);
+    check(ct1p(0xffffff0fffffffffULL), 36);
+}
+
 int main()
 {
     int res;
@@ -468,6 +520,8 @@ int main()
 
     test_l2fetch();
 
+    test_count_trailing_zeros_ones();
+
     puts(err ? "FAIL" : "PASS");
     return err;
 }
-- 
2.25.1

[PATCH] Hexagon (target/hexagon) Merge arguments to probe_pkt_scalar_hvx_stores

[Taylor Simpson]

Reducing the number of arguments reduces the overhead of the helper
call

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
 target/hexagon/helper.h    |  4 ++--
 target/hexagon/translate.h |  1 +
 target/hexagon/op_helper.c |  4 ++--
 target/hexagon/translate.c | 10 +++++-----
 4 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index 368f0b5708..ed7f9842f6 100644
--- a/target/hexagon/helper.h
+++ b/target/hexagon/helper.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -107,4 +107,4 @@ DEF_HELPER_2(vwhist128qm, void, env, s32)
 DEF_HELPER_4(probe_noshuf_load, void, env, i32, int, int)
 DEF_HELPER_2(probe_pkt_scalar_store_s0, void, env, int)
 DEF_HELPER_2(probe_hvx_stores, void, env, int)
-DEF_HELPER_3(probe_pkt_scalar_hvx_stores, void, env, int, int)
+DEF_HELPER_2(probe_pkt_scalar_hvx_stores, void, env, int)
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index db832b0f88..4b9f21c41d 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -178,5 +178,6 @@ FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1,        1, 1)
 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES, 2, 1)
 FIELD(PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED,     3, 1)
 FIELD(PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED,     4, 1)
+FIELD(PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX,        5, 2)
 
 #endif
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index c9a156030e..099c111a8c 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -488,8 +488,7 @@ void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx)
     }
 }
 
-void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask,
-                                         int mmu_idx)
+void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask)
 {
     bool has_st0 = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0);
     bool has_st1 = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1);
@@ -497,6 +496,7 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask,
         FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES);
     bool s0_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED);
     bool s1_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED);
+    int mmu_idx = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX);
 
     if (has_st0) {
         probe_store(env, 0, mmu_idx, s0_is_pred);
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 665476ab48..8c0be5d6a2 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -803,13 +803,11 @@ static void gen_commit_packet(DisasContext *ctx)
         g_assert(!has_store_s1 && !has_hvx_store);
         process_dczeroa(ctx);
     } else if (has_hvx_store) {
-        TCGv mem_idx = tcg_constant_tl(ctx->mem_idx);
-
         if (!has_store_s0 && !has_store_s1) {
+            TCGv mem_idx = tcg_constant_tl(ctx->mem_idx);
             gen_helper_probe_hvx_stores(cpu_env, mem_idx);
         } else {
             int mask = 0;
-            TCGv mask_tcgv;
 
             if (has_store_s0) {
                 mask =
@@ -834,8 +832,10 @@ static void gen_commit_packet(DisasContext *ctx)
                     FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES,
                                S1_IS_PRED, 1);
             }
-            mask_tcgv = tcg_constant_tl(mask);
-            gen_helper_probe_pkt_scalar_hvx_stores(cpu_env, mask_tcgv, mem_idx);
+            mask = FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX,
+                              ctx->mem_idx);
+            gen_helper_probe_pkt_scalar_hvx_stores(cpu_env,
+                                                   tcg_constant_tl(mask));
         }
     } else if (has_store_s0 && has_store_s1) {
         /*
-- 
2.25.1

[PATCH] Hexagon (target/hexagon) Updates to USR should use get_result_gpr

[Taylor Simpson]

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
 target/hexagon/gen_tcg.h                    |  4 +-
 target/hexagon/genptr.h                     | 10 ++---
 target/hexagon/macros.h                     |  8 ----
 target/hexagon/genptr.c                     | 49 ++++++++++-----------
 target/hexagon/idef-parser/parser-helpers.c |  5 ++-
 target/hexagon/idef-parser/idef-parser.y    |  2 +-
 6 files changed, 34 insertions(+), 44 deletions(-)

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index bcf0cf466a..c71df90577 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -1039,11 +1039,11 @@
 
 /* r0 = asr(r1, r2):sat */
 #define fGEN_TCG_S2_asr_r_r_sat(SHORTCODE) \
-    gen_asr_r_r_sat(RdV, RsV, RtV)
+    gen_asr_r_r_sat(ctx, RdV, RsV, RtV)
 
 /* r0 = asl(r1, r2):sat */
 #define fGEN_TCG_S2_asl_r_r_sat(SHORTCODE) \
-    gen_asl_r_r_sat(RdV, RsV, RtV)
+    gen_asl_r_r_sat(ctx, RdV, RsV, RtV)
 
 #define fGEN_TCG_SL2_jumpr31(SHORTCODE) \
     gen_jumpr(ctx, hex_gpr[HEX_REG_LR])
diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h
index 591b059698..76e497aa48 100644
--- a/target/hexagon/genptr.h
+++ b/target/hexagon/genptr.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -37,9 +37,9 @@ TCGv gen_read_reg(TCGv result, int num);
 TCGv gen_read_preg(TCGv pred, uint8_t num);
 void gen_log_reg_write(int rnum, TCGv val);
 void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val);
-void gen_set_usr_field(int field, TCGv val);
-void gen_set_usr_fieldi(int field, int x);
-void gen_set_usr_field_if(int field, TCGv val);
+void gen_set_usr_field(DisasContext *ctx, int field, TCGv val);
+void gen_set_usr_fieldi(DisasContext *ctx, int field, int x);
+void gen_set_usr_field_if(DisasContext *ctx, int field, TCGv val);
 void gen_sat_i32(TCGv dest, TCGv source, int width);
 void gen_sat_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width);
 void gen_satu_i32(TCGv dest, TCGv source, int width);
@@ -48,7 +48,7 @@ void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width);
 void gen_sat_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
 void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width);
 void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
-void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b);
+void gen_add_sat_i64(DisasContext *ctx, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b);
 TCGv gen_8bitsof(TCGv result, TCGv value);
 void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src);
 TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign);
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 482a9c787f..687a289f17 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -48,14 +48,6 @@
 #define TYPE_INT(X)          __builtin_types_compatible_p(typeof(X), int)
 #define TYPE_TCGV(X)         __builtin_types_compatible_p(typeof(X), TCGv)
 #define TYPE_TCGV_I64(X)     __builtin_types_compatible_p(typeof(X), TCGv_i64)
-
-#define SET_USR_FIELD_FUNC(X) \
-    __builtin_choose_expr(TYPE_INT(X), \
-        gen_set_usr_fieldi, \
-        __builtin_choose_expr(TYPE_TCGV(X), \
-            gen_set_usr_field, (void)0))
-#define SET_USR_FIELD(FIELD, VAL) \
-    SET_USR_FIELD_FUNC(VAL)(FIELD, VAL)
 #else
 #define GET_USR_FIELD(FIELD) \
     fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index bb274d4a71..502c85ae35 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -486,30 +486,27 @@ static void gen_write_new_pc_pcrel(DisasContext *ctx, int pc_off,
     }
 }
 
-void gen_set_usr_field(int field, TCGv val)
+void gen_set_usr_field(DisasContext *ctx, int field, TCGv val)
 {
-    tcg_gen_deposit_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR],
-                       val,
+    TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
+    tcg_gen_deposit_tl(usr, usr, val,
                        reg_field_info[field].offset,
                        reg_field_info[field].width);
 }
 
-void gen_set_usr_fieldi(int field, int x)
+void gen_set_usr_fieldi(DisasContext *ctx, int field, int x)
 {
     if (reg_field_info[field].width == 1) {
+        TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
         target_ulong bit = 1 << reg_field_info[field].offset;
         if ((x & 1) == 1) {
-            tcg_gen_ori_tl(hex_new_value[HEX_REG_USR],
-                           hex_new_value[HEX_REG_USR],
-                           bit);
+            tcg_gen_ori_tl(usr, usr, bit);
         } else {
-            tcg_gen_andi_tl(hex_new_value[HEX_REG_USR],
-                            hex_new_value[HEX_REG_USR],
-                            ~bit);
+            tcg_gen_andi_tl(usr, usr, ~bit);
         }
     } else {
         TCGv val = tcg_constant_tl(x);
-        gen_set_usr_field(field, val);
+        gen_set_usr_field(ctx, field, val);
     }
 }
 
@@ -754,7 +751,7 @@ static void gen_endloop0(DisasContext *ctx)
     tcg_gen_brcondi_tl(TCG_COND_EQ, lpcfg, 0, label2);
     {
         tcg_gen_subi_tl(lpcfg, lpcfg, 1);
-        SET_USR_FIELD(USR_LPCFG, lpcfg);
+        gen_set_usr_field(ctx, USR_LPCFG, lpcfg);
     }
     gen_set_label(label2);
 
@@ -829,7 +826,7 @@ static void gen_endloop01(DisasContext *ctx)
     tcg_gen_brcondi_tl(TCG_COND_EQ, lpcfg, 0, label2);
     {
         tcg_gen_subi_tl(lpcfg, lpcfg, 1);
-        SET_USR_FIELD(USR_LPCFG, lpcfg);
+        gen_set_usr_field(ctx, USR_LPCFG, lpcfg);
     }
     gen_set_label(label2);
 
@@ -878,8 +875,9 @@ static void gen_cmpi_jumpnv(DisasContext *ctx,
 }
 
 /* Shift left with saturation */
-static void gen_shl_sat(TCGv dst, TCGv src, TCGv shift_amt)
+static void gen_shl_sat(DisasContext *ctx, TCGv dst, TCGv src, TCGv shift_amt)
 {
+    TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
     TCGv sh32 = tcg_temp_new();
     TCGv dst_sar = tcg_temp_new();
     TCGv ovf = tcg_temp_new();
@@ -911,7 +909,7 @@ static void gen_shl_sat(TCGv dst, TCGv src, TCGv shift_amt)
 
     tcg_gen_setcond_tl(TCG_COND_NE, ovf, dst_sar, src);
     tcg_gen_shli_tl(ovf, ovf, reg_field_info[USR_OVF].offset);
-    tcg_gen_or_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR], ovf);
+    tcg_gen_or_tl(usr, usr, ovf);
 
     tcg_gen_movcond_tl(TCG_COND_EQ, dst, dst_sar, src, dst, satval);
 }
@@ -928,7 +926,7 @@ static void gen_sar(TCGv dst, TCGv src, TCGv shift_amt)
 }
 
 /* Bidirectional shift right with saturation */
-static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
+static void gen_asr_r_r_sat(DisasContext *ctx, TCGv RdV, TCGv RsV, TCGv RtV)
 {
     TCGv shift_amt = tcg_temp_new();
     TCGLabel *positive = gen_new_label();
@@ -939,7 +937,7 @@ static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
 
     /* Negative shift amount => shift left */
     tcg_gen_neg_tl(shift_amt, shift_amt);
-    gen_shl_sat(RdV, RsV, shift_amt);
+    gen_shl_sat(ctx, RdV, RsV, shift_amt);
     tcg_gen_br(done);
 
     gen_set_label(positive);
@@ -950,7 +948,7 @@ static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
 }
 
 /* Bidirectional shift left with saturation */
-static void gen_asl_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
+static void gen_asl_r_r_sat(DisasContext *ctx, TCGv RdV, TCGv RsV, TCGv RtV)
 {
     TCGv shift_amt = tcg_temp_new();
     TCGLabel *positive = gen_new_label();
@@ -966,7 +964,7 @@ static void gen_asl_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
 
     gen_set_label(positive);
     /* Positive shift amount => shift left */
-    gen_shl_sat(RdV, RsV, shift_amt);
+    gen_shl_sat(ctx, RdV, RsV, shift_amt);
 
     gen_set_label(done);
 }
@@ -1109,20 +1107,19 @@ void probe_noshuf_load(TCGv va, int s, int mi)
  * Note: Since this function might branch, `val` is
  * required to be a `tcg_temp_local`.
  */
-void gen_set_usr_field_if(int field, TCGv val)
+void gen_set_usr_field_if(DisasContext *ctx, int field, TCGv val)
 {
     /* Sets the USR field if `val` is non-zero */
     if (reg_field_info[field].width == 1) {
+        TCGv usr = get_result_gpr(ctx, HEX_REG_USR);
         TCGv tmp = tcg_temp_new();
         tcg_gen_extract_tl(tmp, val, 0, reg_field_info[field].width);
         tcg_gen_shli_tl(tmp, tmp, reg_field_info[field].offset);
-        tcg_gen_or_tl(hex_new_value[HEX_REG_USR],
-                      hex_new_value[HEX_REG_USR],
-                      tmp);
+        tcg_gen_or_tl(usr, usr, tmp);
     } else {
         TCGLabel *skip_label = gen_new_label();
         tcg_gen_brcondi_tl(TCG_COND_EQ, val, 0, skip_label);
-        gen_set_usr_field(field, val);
+        gen_set_usr_field(ctx, field, val);
         gen_set_label(skip_label);
     }
 }
@@ -1190,7 +1187,7 @@ void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width)
 }
 
 /* Implements the fADDSAT64 macro in TCG */
-void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
+void gen_add_sat_i64(DisasContext *ctx, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
 {
     TCGv_i64 sum = tcg_temp_new_i64();
     TCGv_i64 xor = tcg_temp_new_i64();
@@ -1227,7 +1224,7 @@ void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
     gen_set_label(ovfl_label);
     tcg_gen_and_i64(cond3, sum, mask);
     tcg_gen_movcond_i64(TCG_COND_NE, ret, cond3, zero, max_pos, max_neg);
-    SET_USR_FIELD(USR_OVF, 1);
+    gen_set_usr_fieldi(ctx, USR_OVF, 1);
 
     gen_set_label(ret_label);
 }
diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/idef-parser/parser-helpers.c
index 18cde6a1be..86511efb62 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -1640,7 +1640,8 @@ void gen_addsat64(Context *c,
 {
     HexValue op1_m = rvalue_materialize(c, locp, op1);
     HexValue op2_m = rvalue_materialize(c, locp, op2);
-    OUT(c, locp, "gen_add_sat_i64(", dst, ", ", &op1_m, ", ", &op2_m, ");\n");
+    OUT(c, locp, "gen_add_sat_i64(ctx, ", dst, ", ", &op1_m, ", ",
+                                  &op2_m, ");\n");
 }
 
 void gen_inst(Context *c, GString *iname)
@@ -1971,7 +1972,7 @@ HexValue gen_rvalue_sat(Context *c, YYLTYPE *locp, HexSat *sat,
     OUT(c, locp, "gen_sat", unsigned_str, "_", bit_suffix, "_ovfl(");
     OUT(c, locp, &ovfl, ", ", &res, ", ", value, ", ", &width->imm.value,
         ");\n");
-    OUT(c, locp, "gen_set_usr_field_if(USR_OVF,", &ovfl, ");\n");
+    OUT(c, locp, "gen_set_usr_field_if(ctx, USR_OVF,", &ovfl, ");\n");
 
     return res;
 }
diff --git a/target/hexagon/idef-parser/idef-parser.y b/target/hexagon/idef-parser/idef-parser.y
index 7d05773b67..5444fd4749 100644
--- a/target/hexagon/idef-parser/idef-parser.y
+++ b/target/hexagon/idef-parser/idef-parser.y
@@ -362,7 +362,7 @@ assign_statement : lvalue '=' rvalue
                                 "Assignment side-effect not modeled!");
                        $3 = gen_rvalue_truncate(c, &@1, &$3);
                        $3 = rvalue_materialize(c, &@1, &$3);
-                       OUT(c, &@1, "SET_USR_FIELD(USR_LPCFG, ", &$3, ");\n");
+                       OUT(c, &@1, "gen_set_usr_field(ctx, USR_LPCFG, ", &$3, ");\n");
                    }
                  | DEPOSIT '(' rvalue ',' rvalue ',' rvalue ')'
                    {
-- 
2.25.1

Re: [PATCH] Hexagon (target/hexagon) Add overrides for count trailing zeros/ones

[Richard Henderson]

On 4/5/23 09:42, Taylor Simpson wrote:
> The following instructions are overriden
>      S2_ct0            Count trailing zeros
>      S2_ct1            Count trailing ones
>      S2_ct0p           Count trailing zeros (register pair)
>      S2_ct1p           Count trailing ones (register pair)
> 
> These instructions are not handled by idef-parser because the
> imported semantics uses bit-reverse.  However, they are
> straightforward to implement in TCG with tcg_gen_ctzi_*
> 
> Test cases added to tests/tcg/hexagon/misc.c
> 
> Signed-off-by: Taylor Simpson<tsimpson@quicinc.com>
> ---
>   target/hexagon/gen_tcg.h | 24 +++++++++++++++++
>   tests/tcg/hexagon/misc.c | 56 +++++++++++++++++++++++++++++++++++++++-
>   2 files changed, 79 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH] Hexagon (target/hexagon) Merge arguments to probe_pkt_scalar_hvx_stores

[Philippe Mathieu-Daudé]

On 5/4/23 18:42, Taylor Simpson wrote:
> Reducing the number of arguments reduces the overhead of the helper
> call
> 
> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
> ---
>   target/hexagon/helper.h    |  4 ++--
>   target/hexagon/translate.h |  1 +
>   target/hexagon/op_helper.c |  4 ++--
>   target/hexagon/translate.c | 10 +++++-----
>   4 files changed, 10 insertions(+), 9 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH] Hexagon (target/hexagon) Updates to USR should use get_result_gpr

[Anton Johansson via]

On 4/5/23 18:42, Taylor Simpson wrote:
> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
> ---
>   target/hexagon/gen_tcg.h                    |  4 +-
>   target/hexagon/genptr.h                     | 10 ++---
>   target/hexagon/macros.h                     |  8 ----
>   target/hexagon/genptr.c                     | 49 ++++++++++-----------
>   target/hexagon/idef-parser/parser-helpers.c |  5 ++-
>   target/hexagon/idef-parser/idef-parser.y    |  2 +-
>   6 files changed, 34 insertions(+), 44 deletions(-)
Reviewed-by: Anton Johansson <anjo@rev.ng>