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([2602:ae:1598:4c01:9456:37ab:20dc:17e1]) by smtp.gmail.com with ESMTPSA id c16-20020a17090ad91000b00265a7145fe5sm1390213pjv.41.2023.07.26.08.01.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Jul 2023 08:01:44 -0700 (PDT) Message-ID: <67a8967e-338a-fbd1-1c06-d5a35f2db509@linaro.org> Date: Wed, 26 Jul 2023 08:01:42 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [RFC PATCH] target/i386: Truncate ESP when exiting from long mode To: Ard Biesheuvel , qemu-devel@nongnu.org Cc: Paolo Bonzini , Eduardo Habkost References: <20230726081710.1051126-1-ardb@kernel.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20230726081710.1051126-1-ardb@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/26/23 01:17, Ard Biesheuvel wrote: > While working on some EFI boot changes for Linux/x86, I noticed that TCG deviates from > bare metal when it comes to how it handles the value of the stack pointer register RSP > when dropping out of long mode. > > On bare metal, RSP is truncated to 32 bits, even if the code that runs in 32-bit > protected mode never uses the stack at all (and uses a long jump rather than long > return to switch back to long mode). This means 64-bit code cannot rely on RSP > surviving any excursions into 32-bit protected mode (with paging disabled). > > Let's align TCG with this behavior, so that code that relies on RSP retaining its value > does not inadvertently work while bare metal does not. > > Observed on Intel Ice Lake cores. > > Cc: Paolo Bonzini Cc: Richard > Henderson Cc: Eduardo Habkost > Link:https://lore.kernel.org/all/20230711091453.2543622-11-ardb@kernel.org/ > Signed-off-by: Ard Biesheuvel --- I used this patch locally to > reproduce an issue that was reported on Ice Lake but didn't trigger in my QEMU > testing. > > Hints welcome on where the architectural behavior is specified, and in particular, > whether or not other 64-bit GPRs can be relied upon to preserve their full 64-bit > length values. No idea about chapter and verse, but it has the feel of being part and parcel with the truncation of eip. While esp is always special, I suspect that none of the GPRs can be relied on carrying all bits. I'm happy with the change though, since similar behaviour can be observed on hw. Acked-by: Richard Henderson r~