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[88.178.97.237]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d188b7555sm2166035e9.16.2025.03.12.16.40.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Mar 2025 16:40:14 -0700 (PDT) Message-ID: <67b33d51-b8c8-421c-8aba-efa9a0b46bf5@linaro.org> Date: Thu, 13 Mar 2025 00:40:13 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 28/38] target/hexagon: Initialize htid, modectl regs To: Brian Cain , qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, quic_mathbern@quicinc.com, ale@rev.ng, anjo@rev.ng, quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com, alex.bennee@linaro.org, quic_mburton@quicinc.com, sidneym@quicinc.com, Brian Cain References: <20250301052628.1011210-1-brian.cain@oss.qualcomm.com> <20250301052628.1011210-29-brian.cain@oss.qualcomm.com> <44e23197-a2ec-4477-a4b8-a526f83e47c2@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 13/3/25 00:10, Brian Cain wrote: > > On 3/12/2025 2:19 PM, Philippe Mathieu-Daudé wrote: >> On 1/3/25 06:26, Brian Cain wrote: >>> From: Brian Cain >>> >>> Signed-off-by: Brian Cain >>> --- >>>   target/hexagon/cpu.c | 8 ++++++++ >>>   1 file changed, 8 insertions(+) >>> >>> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c >>> index 36a93cc22f..2b6a707fca 100644 >>> --- a/target/hexagon/cpu.c >>> +++ b/target/hexagon/cpu.c >>> @@ -26,6 +26,7 @@ >>>   #include "fpu/softfloat-helpers.h" >>>   #include "tcg/tcg.h" >>>   #include "exec/gdbstub.h" >>> +#include "cpu_helper.h" >>>     static void hexagon_v66_cpu_init(Object *obj) { } >>>   static void hexagon_v67_cpu_init(Object *obj) { } >>> @@ -290,11 +291,18 @@ static void hexagon_cpu_reset_hold(Object *obj, >>> ResetType type) >>>       set_float_default_nan_pattern(0b11111111, &env->fp_status); >>>     #ifndef CONFIG_USER_ONLY >>> +    HexagonCPU *cpu = HEXAGON_CPU(cs); >>> + >>>       if (cs->cpu_index == 0) { >> >> This doesn't scale to heterogeneous emulation. >> > > If we have a target-specific index here (instead of cpu_index) guarding > the "g_sreg" allocation shared by these Hexagon vCPUs, does that > suffice?  Or is the problem the shared allocation itself? I'm not sure that suffices, but it is still better from my PoV. Let's assume we instantiate 4 ARM cores, then 2 HEX ones. The first Hexagon core has cpu_index=5. Now for the same example machine we instantiate first the Hexagon cores, then the ARM ones. The first Hexagon core has cpu_index=0. > Could a heterogeneous emulation configuration consist of multiple > instances of (same-architecture) vCPU-groups? Up to you if you want to model multiple hexagon SoCs in the same machine ;) Note in that case you could use a CPUClusterState to group.