From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@opensource.wdc.com>,
qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL v2 00/21] riscv-to-apply queue
Date: Tue, 21 Sep 2021 13:49:22 -0700 [thread overview]
Message-ID: <68032bb6-a669-ba13-6eea-18f39954e6bc@linaro.org> (raw)
In-Reply-To: <20210921065412.312381-1-alistair.francis@opensource.wdc.com>
On 9/20/21 11:53 PM, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit 326ff8dd09556fc2e257196c49f35009700794ac:
>
> Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2021-09-20 16:17:05 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210921
>
> for you to fetch changes up to ed481d9837250aa682f5156528bc923e1b214f76:
>
> hw/riscv: opentitan: Correct the USB Dev address (2021-09-21 12:10:47 +1000)
>
> ----------------------------------------------------------------
> Second RISC-V PR for QEMU 6.2
>
> - ePMP CSR address updates
> - Convert internal interrupts to use QEMU GPIO lines
> - SiFive PWM support
> - Support for RISC-V ACLINT
> - SiFive PDMA fixes
> - Update to u-boot instructions for sifive_u
> - mstatus.SD bug fix for hypervisor extensions
> - OpenTitan fix for USB dev address
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.2
for any user-visible changes.
r~
prev parent reply other threads:[~2021-09-21 20:51 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-21 6:53 [PULL v2 00/21] riscv-to-apply queue Alistair Francis
2021-09-21 6:53 ` [PULL v2 01/21] target/riscv: Update the ePMP CSR address Alistair Francis
2021-09-21 6:53 ` [PULL v2 02/21] target/riscv: Fix satp write Alistair Francis
2021-09-21 6:53 ` [PULL v2 03/21] target/riscv: Expose interrupt pending bits as GPIO lines Alistair Francis
2021-09-21 6:53 ` [PULL v2 04/21] hw/intc: sifive_clint: Use RISC-V CPU " Alistair Francis
2021-09-21 6:53 ` [PULL v2 05/21] hw/intc: ibex_plic: Convert the PLIC to use " Alistair Francis
2021-09-21 6:53 ` [PULL v2 06/21] hw/intc: sifive_plic: " Alistair Francis
2021-09-21 6:53 ` [PULL v2 07/21] hw/intc: ibex_timer: Convert the timer " Alistair Francis
2021-09-21 6:53 ` [PULL v2 08/21] hw/timer: Add SiFive PWM support Alistair Francis
2021-09-21 6:54 ` [PULL v2 09/21] sifive_u: Connect the SiFive PWM device Alistair Francis
2021-09-21 6:54 ` [PULL v2 10/21] hw/intc: Rename sifive_clint sources to riscv_aclint sources Alistair Francis
2021-09-21 6:54 ` [PULL v2 11/21] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Alistair Francis
2021-09-21 6:54 ` [PULL v2 12/21] hw/riscv: virt: Re-factor FDT generation Alistair Francis
2021-09-21 6:54 ` [PULL v2 13/21] hw/riscv: virt: Add optional ACLINT support to virt machine Alistair Francis
2021-09-21 6:54 ` [PULL v2 14/21] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set Alistair Francis
2021-09-21 6:54 ` [PULL v2 15/21] hw/dma: sifive_pdma: claim bit must be set before DMA transactions Alistair Francis
2021-09-21 6:54 ` [PULL v2 16/21] hw/dma: sifive_pdma: allow non-multiple transaction size transactions Alistair Francis
2021-09-21 6:54 ` [PULL v2 17/21] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer Alistair Francis
2021-09-21 6:54 ` [PULL v2 18/21] docs/system/riscv: sifive_u: Update U-Boot instructions Alistair Francis
2021-09-21 6:54 ` [PULL v2 19/21] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped Alistair Francis
2021-09-21 6:54 ` [PULL v2 20/21] target/riscv: csr: Rename HCOUNTEREN_CY and friends Alistair Francis
2021-09-21 6:54 ` [PULL v2 21/21] hw/riscv: opentitan: Correct the USB Dev address Alistair Francis
2021-09-21 20:49 ` Richard Henderson [this message]
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