[PATCH v3 00/12] target/loongarch: Small enhancement about TLB flush

[PATCH v3 00/12] target/loongarch: Small enhancement about TLB flush

[Bibo Mao]

This patch set is continuous MMU enhancement, it is focused on TLB
search, especially on function helper_invtlb_page_asid() and function
helper_invtlb_page_asid_or_g(). The code is similiar with function
loongarch_tlb_search(), one common API loongarch_tlb_search_cb() is
added for these functions.

Also there is optimization with qemu TLB flush, invalidate_tlb_entry()
is used to flush one TLB entry rather than flush all TLB entries.
---
v2 ... v3:
  1. Remove optimization to flush QEMU TLB with MMU_USER_IDX, now both
     MMU_KERNEL_IDX and MMU_USER_IDX bitmap is added.
  2. Add field RESERVE with register CSR_STLBPS, field RESERVE keeps
     zero when change register CSR_STLBPS.

v1 ... v2:
  1. Add bugfix patch with CSR_STLBPS page size set issue.
  2. Add tlb entry invalidation in function invalidate_tlb(), it can be
     used in both helper_invtlb_page_asid() and function
     helper_invtlb_page_asid_or_g().
---
Bibo Mao (12):
  target/loongarch: Use mmu idx bitmap method when flush TLB
  target/loongarch: Add parameter tlb pointer with fill_tlb_entry
  target/loongarch: Reduce TLB flush with helper_tlbwr
  target/loongarch: Update TLB index selection method
  target/loongarch: Fix page size set issue with CSR_STLBPS
  target/loongarch: Add tlb search callback in loongarch_tlb_search()
  target/loongarch: Add common API loongarch_tlb_search_cb()
  target/loongarch: Use loongarch_tlb_search_cb in
    helper_invtlb_page_asid_or_g
  target/loongarch: Use loongarch_tlb_search_cb in
    helper_invtlb_page_asid
  target/loongarch: Invalid tlb entry in invalidate_tlb()
  target/loongarch: Only flush one TLB entry in
    helper_invtlb_page_asid_or_g()
  target/loongarch: Only flush one TLB entry in
    helper_invtlb_page_asid()

 target/loongarch/cpu-csr.h        |   1 +
 target/loongarch/tcg/csr_helper.c |   5 +-
 target/loongarch/tcg/tlb_helper.c | 197 +++++++++++++++++++-----------
 3 files changed, 132 insertions(+), 71 deletions(-)


base-commit: 8415b0619f65bff12f10c774659df92d3f61daca
-- 
2.39.3

[PATCH v3 01/12] target/loongarch: Use mmu idx bitmap method when flush TLB

[Bibo Mao]

With API tlb_flush_range_by_mmuidx(), bitmap of mmu idx should be used
rather than itself. Also MMU_KERNEL_IDX and MMU_USER_IDX are used rather
than current running mmu idx when flush TLB.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/tcg/tlb_helper.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 9365860c8c..d58f447555 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -101,8 +101,7 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
     target_ulong addr, mask, pagesize;
     uint8_t tlb_ps;
     LoongArchTLB *tlb = &env->tlb[index];
-
-    int mmu_idx = cpu_mmu_index(env_cpu(env), false);
+    int mmu_idx = BIT(MMU_KERNEL_IDX) | BIT(MMU_USER_IDX);
     uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V);
     uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V);
     uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
-- 
2.39.3

Re: [PATCH v3 01/12] target/loongarch: Use mmu idx bitmap method when flush TLB

[Richard Henderson]

On 9/3/25 10:48, Bibo Mao wrote:
> With API tlb_flush_range_by_mmuidx(), bitmap of mmu idx should be used
> rather than itself. Also MMU_KERNEL_IDX and MMU_USER_IDX are used rather
> than current running mmu idx when flush TLB.
> 
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>   target/loongarch/tcg/tlb_helper.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
> index 9365860c8c..d58f447555 100644
> --- a/target/loongarch/tcg/tlb_helper.c
> +++ b/target/loongarch/tcg/tlb_helper.c
> @@ -101,8 +101,7 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
>       target_ulong addr, mask, pagesize;
>       uint8_t tlb_ps;
>       LoongArchTLB *tlb = &env->tlb[index];
> -
> -    int mmu_idx = cpu_mmu_index(env_cpu(env), false);
> +    int mmu_idx = BIT(MMU_KERNEL_IDX) | BIT(MMU_USER_IDX);
>       uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V);
>       uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V);
>       uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);

Better to rename the variable too, since this isn't an mmu_idx.
We have used "idxmap" elsewhere for this purpose.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH v3 01/12] target/loongarch: Use mmu idx bitmap method when flush TLB

[Bibo Mao]

On 2025/9/3 下午9:02, Richard Henderson wrote:
> On 9/3/25 10:48, Bibo Mao wrote:
>> With API tlb_flush_range_by_mmuidx(), bitmap of mmu idx should be used
>> rather than itself. Also MMU_KERNEL_IDX and MMU_USER_IDX are used rather
>> than current running mmu idx when flush TLB.
>>
>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>> ---
>>   target/loongarch/tcg/tlb_helper.c | 3 +--
>>   1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/target/loongarch/tcg/tlb_helper.c 
>> b/target/loongarch/tcg/tlb_helper.c
>> index 9365860c8c..d58f447555 100644
>> --- a/target/loongarch/tcg/tlb_helper.c
>> +++ b/target/loongarch/tcg/tlb_helper.c
>> @@ -101,8 +101,7 @@ static void invalidate_tlb_entry(CPULoongArchState 
>> *env, int index)
>>       target_ulong addr, mask, pagesize;
>>       uint8_t tlb_ps;
>>       LoongArchTLB *tlb = &env->tlb[index];
>> -
>> -    int mmu_idx = cpu_mmu_index(env_cpu(env), false);
>> +    int mmu_idx = BIT(MMU_KERNEL_IDX) | BIT(MMU_USER_IDX);
>>       uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V);
>>       uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V);
>>       uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
> 
> Better to rename the variable too, since this isn't an mmu_idx.
> We have used "idxmap" elsewhere for this purpose.
sure, will use idxmap in next version.

Regards
Bibo Mao
> 
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> 
> 
> r~

[PATCH v3 02/12] target/loongarch: Add parameter tlb pointer with fill_tlb_entry

[Bibo Mao]

With function fill_tlb_entry(), it will update LoongArch emulated
TLB information. Here parameter tlb pointer is added so that TLB
entry will be updated based on relative TLB CSR registers.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/loongarch/tcg/tlb_helper.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index d58f447555..fcd03ca320 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -143,9 +143,8 @@ static void invalidate_tlb(CPULoongArchState *env, int index)
     invalidate_tlb_entry(env, index);
 }
 
-static void fill_tlb_entry(CPULoongArchState *env, int index)
+static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb)
 {
-    LoongArchTLB *tlb = &env->tlb[index];
     uint64_t lo0, lo1, csr_vppn;
     uint16_t csr_asid;
     uint8_t csr_ps;
@@ -312,7 +311,7 @@ void helper_tlbwr(CPULoongArchState *env)
         return;
     }
 
-    fill_tlb_entry(env, index);
+    fill_tlb_entry(env, env->tlb + index);
 }
 
 void helper_tlbfill(CPULoongArchState *env)
@@ -350,7 +349,7 @@ void helper_tlbfill(CPULoongArchState *env)
     }
 
     invalidate_tlb(env, index);
-    fill_tlb_entry(env, index);
+    fill_tlb_entry(env, env->tlb + index);
 }
 
 void helper_tlbclr(CPULoongArchState *env)
-- 
2.39.3

[PATCH v3 03/12] target/loongarch: Reduce TLB flush with helper_tlbwr

[Bibo Mao]

With function helper_tlbwr(), specified LoongArch TLB entry will be
updated. There are two PTE pages in one TLB entry called even/odd
pages. Supposing even/odd page is normal/none state, when odd page
is added, TLB entry is changed as normal/normal state and even page
keeps unchanged.

In this situation, it is not necessary to flush QEMU TLB since even
page keep unchanged and odd page is newly changed. Here check whether
PTE page is the same or not, TLB flush can be skipped if both are the
same or newly added.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/tcg/tlb_helper.c | 33 ++++++++++++++++++++++++++-----
 1 file changed, 28 insertions(+), 5 deletions(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index fcd03ca320..331b485b1a 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -302,16 +302,39 @@ void helper_tlbrd(CPULoongArchState *env)
 void helper_tlbwr(CPULoongArchState *env)
 {
     int index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
+    LoongArchTLB *old, new;
+    bool skip_inv = false;
+    uint8_t tlb_v0, tlb_v1;
 
-    invalidate_tlb(env, index);
-
+    old = env->tlb + index;
     if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) {
-        env->tlb[index].tlb_misc = FIELD_DP64(env->tlb[index].tlb_misc,
-                                              TLB_MISC, E, 0);
+        invalidate_tlb(env, index);
+        old->tlb_misc = FIELD_DP64(old->tlb_misc, TLB_MISC, E, 0);
         return;
     }
 
-    fill_tlb_entry(env, env->tlb + index);
+    new.tlb_misc = 0;
+    new.tlb_entry0 = 0;
+    new.tlb_entry1 = 0;
+    fill_tlb_entry(env, &new);
+    /* Check whether ASID/VPPN is the same */
+    if (old->tlb_misc == new.tlb_misc) {
+        /* Check whether both even/odd pages is the same or invalid */
+        tlb_v0 = FIELD_EX64(old->tlb_entry0, TLBENTRY, V);
+        tlb_v1 = FIELD_EX64(old->tlb_entry1, TLBENTRY, V);
+        if ((!tlb_v0 || new.tlb_entry0 == old->tlb_entry0) &&
+            (!tlb_v1 || new.tlb_entry1 == old->tlb_entry1)) {
+            skip_inv = true;
+        }
+    }
+
+    /* flush tlb before updating the entry */
+    if (!skip_inv) {
+        invalidate_tlb(env, index);
+    }
+    old->tlb_misc = new.tlb_misc;
+    old->tlb_entry0 = new.tlb_entry0;
+    old->tlb_entry1 = new.tlb_entry1;
 }
 
 void helper_tlbfill(CPULoongArchState *env)
-- 
2.39.3

Re: [PATCH v3 03/12] target/loongarch: Reduce TLB flush with helper_tlbwr

[Richard Henderson]

On 9/3/25 10:48, Bibo Mao wrote:
> With function helper_tlbwr(), specified LoongArch TLB entry will be
> updated. There are two PTE pages in one TLB entry called even/odd
> pages. Supposing even/odd page is normal/none state, when odd page
> is added, TLB entry is changed as normal/normal state and even page
> keeps unchanged.
> 
> In this situation, it is not necessary to flush QEMU TLB since even
> page keep unchanged and odd page is newly changed. Here check whether
> PTE page is the same or not, TLB flush can be skipped if both are the
> same or newly added.
> 
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>   target/loongarch/tcg/tlb_helper.c | 33 ++++++++++++++++++++++++++-----
>   1 file changed, 28 insertions(+), 5 deletions(-)
> 
> diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
> index fcd03ca320..331b485b1a 100644
> --- a/target/loongarch/tcg/tlb_helper.c
> +++ b/target/loongarch/tcg/tlb_helper.c
> @@ -302,16 +302,39 @@ void helper_tlbrd(CPULoongArchState *env)
>   void helper_tlbwr(CPULoongArchState *env)
>   {
>       int index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
> +    LoongArchTLB *old, new;

Perhaps "new = { }", then ...

> +    new.tlb_misc = 0;
> +    new.tlb_entry0 = 0;
> +    new.tlb_entry1 = 0;

... this is unnecessary.

> +    fill_tlb_entry(env, &new);
> +    /* Check whether ASID/VPPN is the same */
> +    if (old->tlb_misc == new.tlb_misc) {
> +        /* Check whether both even/odd pages is the same or invalid */
> +        tlb_v0 = FIELD_EX64(old->tlb_entry0, TLBENTRY, V);
> +        tlb_v1 = FIELD_EX64(old->tlb_entry1, TLBENTRY, V);
> +        if ((!tlb_v0 || new.tlb_entry0 == old->tlb_entry0) &&
> +            (!tlb_v1 || new.tlb_entry1 == old->tlb_entry1)) {
> +            skip_inv = true;
> +        }
> +    }
> +
> +    /* flush tlb before updating the entry */
> +    if (!skip_inv) {
> +        invalidate_tlb(env, index);
> +    }
> +    old->tlb_misc = new.tlb_misc;
> +    old->tlb_entry0 = new.tlb_entry0;
> +    old->tlb_entry1 = new.tlb_entry1;

Perhaps better as "*old = new".

Anyway,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH v3 03/12] target/loongarch: Reduce TLB flush with helper_tlbwr

[Bibo Mao]

On 2025/9/3 下午9:07, Richard Henderson wrote:
> On 9/3/25 10:48, Bibo Mao wrote:
>> With function helper_tlbwr(), specified LoongArch TLB entry will be
>> updated. There are two PTE pages in one TLB entry called even/odd
>> pages. Supposing even/odd page is normal/none state, when odd page
>> is added, TLB entry is changed as normal/normal state and even page
>> keeps unchanged.
>>
>> In this situation, it is not necessary to flush QEMU TLB since even
>> page keep unchanged and odd page is newly changed. Here check whether
>> PTE page is the same or not, TLB flush can be skipped if both are the
>> same or newly added.
>>
>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>> ---
>>   target/loongarch/tcg/tlb_helper.c | 33 ++++++++++++++++++++++++++-----
>>   1 file changed, 28 insertions(+), 5 deletions(-)
>>
>> diff --git a/target/loongarch/tcg/tlb_helper.c 
>> b/target/loongarch/tcg/tlb_helper.c
>> index fcd03ca320..331b485b1a 100644
>> --- a/target/loongarch/tcg/tlb_helper.c
>> +++ b/target/loongarch/tcg/tlb_helper.c
>> @@ -302,16 +302,39 @@ void helper_tlbrd(CPULoongArchState *env)
>>   void helper_tlbwr(CPULoongArchState *env)
>>   {
>>       int index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
>> +    LoongArchTLB *old, new;
> 
> Perhaps "new = { }", then ...
> 
>> +    new.tlb_misc = 0;
>> +    new.tlb_entry0 = 0;
>> +    new.tlb_entry1 = 0;
> 
> ... this is unnecessary.
yes, this is simpler with { }.  Will do.
> 
>> +    fill_tlb_entry(env, &new);
>> +    /* Check whether ASID/VPPN is the same */
>> +    if (old->tlb_misc == new.tlb_misc) {
>> +        /* Check whether both even/odd pages is the same or invalid */
>> +        tlb_v0 = FIELD_EX64(old->tlb_entry0, TLBENTRY, V);
>> +        tlb_v1 = FIELD_EX64(old->tlb_entry1, TLBENTRY, V);
>> +        if ((!tlb_v0 || new.tlb_entry0 == old->tlb_entry0) &&
>> +            (!tlb_v1 || new.tlb_entry1 == old->tlb_entry1)) {
>> +            skip_inv = true;
>> +        }
>> +    }
>> +
>> +    /* flush tlb before updating the entry */
>> +    if (!skip_inv) {
>> +        invalidate_tlb(env, index);
>> +    }
>> +    old->tlb_misc = new.tlb_misc;
>> +    old->tlb_entry0 = new.tlb_entry0;
>> +    old->tlb_entry1 = new.tlb_entry1;
> 
> Perhaps better as "*old = new".
Will do in this way.

Regards
Bibo Mao
> 
> Anyway,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> 
> 
> r~

[PATCH v3 04/12] target/loongarch: Update TLB index selection method

[Bibo Mao]

With function helper_tlbfill(), since there is no suitable TLB entry,
new TLB will be added and invalidate one old TLB entry. The old TLB
entry index is selected randomly, instead it can be optimized as
following:
  1. invalid TLB entry can be selected at first.
  2. TLB entry with other ASID can be selected secondly
  3. random method is used by last.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/tcg/tlb_helper.c | 49 ++++++++++++++++++++++++++-----
 1 file changed, 42 insertions(+), 7 deletions(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 331b485b1a..00422f259d 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -340,8 +340,11 @@ void helper_tlbwr(CPULoongArchState *env)
 void helper_tlbfill(CPULoongArchState *env)
 {
     uint64_t address, entryhi;
-    int index, set, stlb_idx;
+    int index, set, i, stlb_idx;
     uint16_t pagesize, stlb_ps;
+    uint16_t asid, tlb_asid;
+    LoongArchTLB *tlb;
+    uint8_t tlb_e;
 
     if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
         entryhi = env->CSR_TLBREHI;
@@ -355,20 +358,52 @@ void helper_tlbfill(CPULoongArchState *env)
 
     /* Validity of stlb_ps is checked in helper_csrwr_stlbps() */
     stlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+    asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
     if (pagesize == stlb_ps) {
         /* Only write into STLB bits [47:13] */
         address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT);
-
-        /* Choose one set ramdomly */
-        set = get_random_tlb(0, 7);
-
-        /* Index in one set */
+        set = -1;
         stlb_idx = (address >> (stlb_ps + 1)) & 0xff; /* [0,255] */
+        for (i = 0; i < 8; ++i) {
+            tlb = &env->tlb[i * 256 + stlb_idx];
+            tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
+            if (!tlb_e) {
+                set = i;
+                break;
+            }
+
+            tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
+            if (asid != tlb_asid) {
+                set = i;
+            }
+        }
 
+        /* Choose one set randomly */
+        if (set < 0) {
+            set = get_random_tlb(0, 7);
+        }
         index = set * 256 + stlb_idx;
     } else {
         /* Only write into MTLB */
-        index = get_random_tlb(LOONGARCH_STLB, LOONGARCH_TLB_MAX - 1);
+        index = -1;
+        for (i = LOONGARCH_STLB; i < LOONGARCH_TLB_MAX; i++) {
+            tlb = &env->tlb[i];
+            tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
+
+            if (!tlb_e) {
+                index = i;
+                break;
+            }
+
+            tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
+            if (asid != tlb_asid) {
+                index = i;
+            }
+        }
+
+        if (index < 0) {
+            index = get_random_tlb(LOONGARCH_STLB, LOONGARCH_TLB_MAX - 1);
+        }
     }
 
     invalidate_tlb(env, index);
-- 
2.39.3

Re: [PATCH v3 04/12] target/loongarch: Update TLB index selection method

[Richard Henderson]

On 9/3/25 10:48, Bibo Mao wrote:
> With function helper_tlbfill(), since there is no suitable TLB entry,
> new TLB will be added and invalidate one old TLB entry. The old TLB
> entry index is selected randomly, instead it can be optimized as
> following:
>    1. invalid TLB entry can be selected at first.
>    2. TLB entry with other ASID can be selected secondly
>    3. random method is used by last.
> 
> Signed-off-by: Bibo Mao<maobibo@loongson.cn>
> ---
>   target/loongarch/tcg/tlb_helper.c | 49 ++++++++++++++++++++++++++-----
>   1 file changed, 42 insertions(+), 7 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH v3 05/12] target/loongarch: Fix page size set issue with CSR_STLBPS

[Bibo Mao]

When modify register CSR_STLBPS, the page size should come from
input parameter rather than old value.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/cpu-csr.h        | 1 +
 target/loongarch/tcg/csr_helper.c | 5 +++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index 0834e91f30..1a311bf06a 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -106,6 +106,7 @@ FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6)
 
 #define LOONGARCH_CSR_STLBPS         0x1e /* Stlb page size */
 FIELD(CSR_STLBPS, PS, 0, 5)
+FIELD(CSR_STLBPS, RESERVE, 5, 27)
 
 #define LOONGARCH_CSR_RVACFG         0x1f /* Reduced virtual address config */
 FIELD(CSR_RVACFG, RBITS, 0, 4)
diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c
index 0d99e2c92b..eb60fefa82 100644
--- a/target/loongarch/tcg/csr_helper.c
+++ b/target/loongarch/tcg/csr_helper.c
@@ -26,13 +26,14 @@ target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val)
      * The real hardware only supports the min tlb_ps is 12
      * tlb_ps=0 may cause undefined-behavior.
      */
-    uint8_t tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+    uint8_t tlb_ps = FIELD_EX64(val, CSR_STLBPS, PS);
     if (!check_ps(env, tlb_ps)) {
         qemu_log_mask(LOG_GUEST_ERROR,
                       "Attempted set ps %d\n", tlb_ps);
     } else {
         /* Only update PS field, reserved bit keeps zero */
-        env->CSR_STLBPS = FIELD_DP64(old_v, CSR_STLBPS, PS, tlb_ps);
+        val = FIELD_DP64(val, CSR_STLBPS, RESERVE, 0);
+        env->CSR_STLBPS = val;
     }
 
     return old_v;
-- 
2.39.3

[PATCH v3 06/12] target/loongarch: Add tlb search callback in loongarch_tlb_search()

[Bibo Mao]

With function loongarch_tlb_search(), it is to search TLB entry with
speficied virtual address, the difference is selection with asid and
global bit. Here add selection callback with asid and global bit.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/tcg/tlb_helper.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 00422f259d..006fe1b207 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -21,6 +21,17 @@
 #include "cpu-csr.h"
 #include "tcg/tcg_loongarch.h"
 
+typedef bool (*tlb_match)(int global, int asid, int tlb_asid);
+
+static bool tlb_match_any(int global, int asid, int tlb_asid)
+{
+    if (global == 1 || tlb_asid == asid) {
+        return true;
+    }
+
+    return false;
+}
+
 bool check_ps(CPULoongArchState *env, uint8_t tlb_ps)
 {
     if (tlb_ps >= 64) {
@@ -204,9 +215,11 @@ static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
     uint8_t tlb_e, tlb_ps, tlb_g, stlb_ps;
     int i, compare_shift;
     uint64_t vpn, tlb_vppn;
+    tlb_match func;
 
+    func = tlb_match_any;
     csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
-   stlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+    stlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
     vpn = (vaddr & TARGET_VIRT_MASK) >> (stlb_ps + 1);
     stlb_idx = vpn & 0xff; /* VA[25:15] <==> TLBIDX.index for 16KiB Page */
     compare_shift = stlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
@@ -220,7 +233,7 @@ static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
             tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
             tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
 
-            if ((tlb_g == 1 || tlb_asid == csr_asid) &&
+            if (func(tlb_g, csr_asid, tlb_asid) &&
                 (vpn == (tlb_vppn >> compare_shift))) {
                 *index = i * 256 + stlb_idx;
                 return true;
@@ -239,7 +252,7 @@ static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
             tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
             compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
             vpn = (vaddr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
-            if ((tlb_g == 1 || tlb_asid == csr_asid) &&
+            if (func(tlb_g, csr_asid, tlb_asid) &&
                 (vpn == (tlb_vppn >> compare_shift))) {
                 *index = i;
                 return true;
-- 
2.39.3

Re: [PATCH v3 06/12] target/loongarch: Add tlb search callback in loongarch_tlb_search()

[Richard Henderson]

On 9/3/25 10:48, Bibo Mao wrote:
> With function loongarch_tlb_search(), it is to search TLB entry with
> speficied virtual address, the difference is selection with asid and
> global bit. Here add selection callback with asid and global bit.
> 
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>   target/loongarch/tcg/tlb_helper.c | 19 ++++++++++++++++---
>   1 file changed, 16 insertions(+), 3 deletions(-)
> 
> diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
> index 00422f259d..006fe1b207 100644
> --- a/target/loongarch/tcg/tlb_helper.c
> +++ b/target/loongarch/tcg/tlb_helper.c
> @@ -21,6 +21,17 @@
>   #include "cpu-csr.h"
>   #include "tcg/tcg_loongarch.h"
>   
> +typedef bool (*tlb_match)(int global, int asid, int tlb_asid);

Should global parameter be bool?

> +
> +static bool tlb_match_any(int global, int asid, int tlb_asid)
> +{
> +    if (global == 1 || tlb_asid == asid) {
> +        return true;
> +    }
> +
> +    return false;
> +}

More compact as

     return global || tlb_asid == asid;

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH v3 06/12] target/loongarch: Add tlb search callback in loongarch_tlb_search()

[Bibo Mao]

On 2025/9/3 下午9:14, Richard Henderson wrote:
> On 9/3/25 10:48, Bibo Mao wrote:
>> With function loongarch_tlb_search(), it is to search TLB entry with
>> speficied virtual address, the difference is selection with asid and
>> global bit. Here add selection callback with asid and global bit.
>>
>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>> ---
>>   target/loongarch/tcg/tlb_helper.c | 19 ++++++++++++++++---
>>   1 file changed, 16 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/loongarch/tcg/tlb_helper.c 
>> b/target/loongarch/tcg/tlb_helper.c
>> index 00422f259d..006fe1b207 100644
>> --- a/target/loongarch/tcg/tlb_helper.c
>> +++ b/target/loongarch/tcg/tlb_helper.c
>> @@ -21,6 +21,17 @@
>>   #include "cpu-csr.h"
>>   #include "tcg/tcg_loongarch.h"
>> +typedef bool (*tlb_match)(int global, int asid, int tlb_asid);
> 
> Should global parameter be bool?
Will do.
> 
>> +
>> +static bool tlb_match_any(int global, int asid, int tlb_asid)
>> +{
>> +    if (global == 1 || tlb_asid == asid) {
>> +        return true;
>> +    }
>> +
>> +    return false;
>> +}
> 
> More compact as
> 
>      return global || tlb_asid == asid;
yes, this is better. Will do in next version.

Regards
Bibo Mao
> 
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> 
> 
> r~

[PATCH v3 07/12] target/loongarch: Add common API loongarch_tlb_search_cb()

[Bibo Mao]

Common API loongarch_tlb_search_cb() is added here to search TLB entry
with specified address.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/tcg/tlb_helper.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 006fe1b207..fc853f6e80 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -207,18 +207,16 @@ static uint32_t get_random_tlb(uint32_t low, uint32_t high)
  * field in tlb entry contains bit[47:13], so need adjust.
  * virt_vpn = vaddr[47:13]
  */
-static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
-                                 int *index)
+static bool loongarch_tlb_search_cb(CPULoongArchState *env, vaddr vaddr,
+                                    int *index, int asid, tlb_match func)
 {
     LoongArchTLB *tlb;
     uint16_t csr_asid, tlb_asid, stlb_idx;
     uint8_t tlb_e, tlb_ps, tlb_g, stlb_ps;
     int i, compare_shift;
     uint64_t vpn, tlb_vppn;
-    tlb_match func;
 
-    func = tlb_match_any;
-    csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
+    csr_asid = asid;
     stlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
     vpn = (vaddr & TARGET_VIRT_MASK) >> (stlb_ps + 1);
     stlb_idx = vpn & 0xff; /* VA[25:15] <==> TLBIDX.index for 16KiB Page */
@@ -262,6 +260,17 @@ static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
     return false;
 }
 
+static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
+                                 int *index)
+{
+    int asid;
+    tlb_match func;
+
+    func = tlb_match_any;
+    asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
+    return loongarch_tlb_search_cb(env, vaddr, index, asid, func);
+}
+
 void helper_tlbsrch(CPULoongArchState *env)
 {
     int index, match;
-- 
2.39.3

Re: [PATCH v3 07/12] target/loongarch: Add common API loongarch_tlb_search_cb()

[Richard Henderson]

On 9/3/25 10:48, Bibo Mao wrote:
> Common API loongarch_tlb_search_cb() is added here to search TLB entry
> with specified address.
> 
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>   target/loongarch/tcg/tlb_helper.c | 19 ++++++++++++++-----
>   1 file changed, 14 insertions(+), 5 deletions(-)
> 
> diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
> index 006fe1b207..fc853f6e80 100644
> --- a/target/loongarch/tcg/tlb_helper.c
> +++ b/target/loongarch/tcg/tlb_helper.c
> @@ -207,18 +207,16 @@ static uint32_t get_random_tlb(uint32_t low, uint32_t high)
>    * field in tlb entry contains bit[47:13], so need adjust.
>    * virt_vpn = vaddr[47:13]
>    */
> -static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
> -                                 int *index)
> +static bool loongarch_tlb_search_cb(CPULoongArchState *env, vaddr vaddr,
> +                                    int *index, int asid, tlb_match func)

Name the parameter csr_asid, then

>   {
>       LoongArchTLB *tlb;
>       uint16_t csr_asid, tlb_asid, stlb_idx;
>       uint8_t tlb_e, tlb_ps, tlb_g, stlb_ps;
>       int i, compare_shift;
>       uint64_t vpn, tlb_vppn;
> -    tlb_match func;
>   
> -    func = tlb_match_any;
> -    csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
> +    csr_asid = asid;

this is unnecessary.

Anyway,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

[PATCH v3 08/12] target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid_or_g

[Bibo Mao]

With function helper_invtlb_page_asid_or_g(), currently it is to
search TLB entry one by one. Instead STLB can be searched at first
with hash method, and then search MTLB with one by one method.

Here common API loongarch_tlb_search_cb() is used in function
helper_invtlb_page_asid_or_g().

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/tcg/tlb_helper.c | 33 +++++++++++--------------------
 1 file changed, 11 insertions(+), 22 deletions(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index fc853f6e80..620de85a3a 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -561,30 +561,19 @@ void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
 void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
                                   target_ulong info, target_ulong addr)
 {
-    uint16_t asid = info & 0x3ff;
-
-    for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
-        LoongArchTLB *tlb = &env->tlb[i];
-        uint8_t tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
-        uint16_t tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
-        uint64_t vpn, tlb_vppn;
-        uint8_t tlb_ps, compare_shift;
-        uint8_t tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
-
-        if (!tlb_e) {
-            continue;
-        }
-
-        tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
-        tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
-        vpn = (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
-        compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
+    int index, asid = info & 0x3ff;
+    LoongArchTLB *tlb;
+    tlb_match func;
+    bool ret;
 
-        if ((tlb_g || (tlb_asid == asid)) &&
-            (vpn == (tlb_vppn >> compare_shift))) {
-            tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
-        }
+    func = tlb_match_any;
+    ret = loongarch_tlb_search_cb(env, addr, &index, asid, func);
+    if (!ret) {
+        return;
     }
+
+    tlb = &env->tlb[index];
+    tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
     tlb_flush(env_cpu(env));
 }
 
-- 
2.39.3

Re: [PATCH v3 08/12] target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid_or_g

[Richard Henderson]

On 9/3/25 10:48, Bibo Mao wrote:
> +    ret = loongarch_tlb_search_cb(env, addr, &index, asid, func);
> +    if (!ret) {
> +        return;
>       }
> +
> +    tlb = &env->tlb[index];

Perhaps it would be better to have loongarch_tlb_search_cb return the LoongArchTLB 
pointer, or NULL for no match.

Anyway,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH v3 08/12] target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid_or_g

[Bibo Mao]

On 2025/9/3 下午9:20, Richard Henderson wrote:
> On 9/3/25 10:48, Bibo Mao wrote:
>> +    ret = loongarch_tlb_search_cb(env, addr, &index, asid, func);
>> +    if (!ret) {
>> +        return;
>>       }
>> +
>> +    tlb = &env->tlb[index];
> 
> Perhaps it would be better to have loongarch_tlb_search_cb return the 
> LoongArchTLB pointer, or NULL for no match.
Sure, will add separate patch to have loongarch_tlb_search_cb return the
LoongArchTLB pointer.

Regards
Bibo Mao
> 
> Anyway,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> 
> 
> r~

[PATCH v3 09/12] target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid

[Bibo Mao]

With function helper_invtlb_page_asid(), currently it is to search
TLB entry one by one. Instead STLB can be searched at first with hash
method, and then search MTLB with one by one method

Here common API loongarch_tlb_search_cb() is used in function
helper_invtlb_page_asid()

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/tcg/tlb_helper.c | 42 +++++++++++++++----------------
 1 file changed, 20 insertions(+), 22 deletions(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 620de85a3a..c074c956a2 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -32,6 +32,15 @@ static bool tlb_match_any(int global, int asid, int tlb_asid)
     return false;
 }
 
+static bool tlb_match_asid(int global, int asid, int tlb_asid)
+{
+    if (!global && tlb_asid == asid) {
+        return true;
+    }
+
+    return false;
+}
+
 bool check_ps(CPULoongArchState *env, uint8_t tlb_ps)
 {
     if (tlb_ps >= 64) {
@@ -531,30 +540,19 @@ void helper_invtlb_all_asid(CPULoongArchState *env, target_ulong info)
 void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
                              target_ulong addr)
 {
-    uint16_t asid = info & 0x3ff;
-
-    for (int i = 0; i < LOONGARCH_TLB_MAX; i++) {
-        LoongArchTLB *tlb = &env->tlb[i];
-        uint8_t tlb_g = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G);
-        uint16_t tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
-        uint64_t vpn, tlb_vppn;
-        uint8_t tlb_ps, compare_shift;
-        uint8_t tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
-
-        if (!tlb_e) {
-            continue;
-        }
-
-        tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
-        tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
-        vpn = (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
-        compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
+    int index, asid = info & 0x3ff;
+    LoongArchTLB *tlb;
+    tlb_match func;
+    bool ret;
 
-        if (!tlb_g && (tlb_asid == asid) &&
-           (vpn == (tlb_vppn >> compare_shift))) {
-            tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
-        }
+    func = tlb_match_asid;
+    ret = loongarch_tlb_search_cb(env, addr, &index, asid, func);
+    if (!ret) {
+        return;
     }
+
+    tlb = &env->tlb[index];
+    tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
     tlb_flush(env_cpu(env));
 }
 
-- 
2.39.3

Re: [PATCH v3 09/12] target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid

[Richard Henderson]

On 9/3/25 10:48, Bibo Mao wrote:
> With function helper_invtlb_page_asid(), currently it is to search
> TLB entry one by one. Instead STLB can be searched at first with hash
> method, and then search MTLB with one by one method
> 
> Here common API loongarch_tlb_search_cb() is used in function
> helper_invtlb_page_asid()
> 
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>   target/loongarch/tcg/tlb_helper.c | 42 +++++++++++++++----------------
>   1 file changed, 20 insertions(+), 22 deletions(-)
> 
> diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
> index 620de85a3a..c074c956a2 100644
> --- a/target/loongarch/tcg/tlb_helper.c
> +++ b/target/loongarch/tcg/tlb_helper.c
> @@ -32,6 +32,15 @@ static bool tlb_match_any(int global, int asid, int tlb_asid)
>       return false;
>   }
>   
> +static bool tlb_match_asid(int global, int asid, int tlb_asid)
> +{
> +    if (!global && tlb_asid == asid) {
> +        return true;
> +    }
> +
> +    return false;

return !global && tlb_asid == asid;

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH v3 09/12] target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid

[Bibo Mao]

On 2025/9/3 下午9:21, Richard Henderson wrote:
> On 9/3/25 10:48, Bibo Mao wrote:
>> With function helper_invtlb_page_asid(), currently it is to search
>> TLB entry one by one. Instead STLB can be searched at first with hash
>> method, and then search MTLB with one by one method
>>
>> Here common API loongarch_tlb_search_cb() is used in function
>> helper_invtlb_page_asid()
>>
>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>> ---
>>   target/loongarch/tcg/tlb_helper.c | 42 +++++++++++++++----------------
>>   1 file changed, 20 insertions(+), 22 deletions(-)
>>
>> diff --git a/target/loongarch/tcg/tlb_helper.c 
>> b/target/loongarch/tcg/tlb_helper.c
>> index 620de85a3a..c074c956a2 100644
>> --- a/target/loongarch/tcg/tlb_helper.c
>> +++ b/target/loongarch/tcg/tlb_helper.c
>> @@ -32,6 +32,15 @@ static bool tlb_match_any(int global, int asid, int 
>> tlb_asid)
>>       return false;
>>   }
>> +static bool tlb_match_asid(int global, int asid, int tlb_asid)
>> +{
>> +    if (!global && tlb_asid == asid) {
>> +        return true;
>> +    }
>> +
>> +    return false;
> 
> return !global && tlb_asid == asid;
will do.

Regards
Bibo Mao
> 
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> 
> 
> r~

[PATCH v3 10/12] target/loongarch: Invalid tlb entry in invalidate_tlb()

[Bibo Mao]

Invalid tlb entry in function invalidate_tlb(), and its usage is
simple and easy to use.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/tcg/tlb_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index c074c956a2..ee40684a18 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -161,6 +161,7 @@ static void invalidate_tlb(CPULoongArchState *env, int index)
         return;
     }
     invalidate_tlb_entry(env, index);
+    tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
 }
 
 static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb)
@@ -340,7 +341,6 @@ void helper_tlbwr(CPULoongArchState *env)
     old = env->tlb + index;
     if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) {
         invalidate_tlb(env, index);
-        old->tlb_misc = FIELD_DP64(old->tlb_misc, TLB_MISC, E, 0);
         return;
     }
 
-- 
2.39.3

Re: [PATCH v3 10/12] target/loongarch: Invalid tlb entry in invalidate_tlb()

[Richard Henderson]

On 9/3/25 10:48, Bibo Mao wrote:
> Invalid tlb entry in function invalidate_tlb(), and its usage is
> simple and easy to use.
> 
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>   target/loongarch/tcg/tlb_helper.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
> index c074c956a2..ee40684a18 100644
> --- a/target/loongarch/tcg/tlb_helper.c
> +++ b/target/loongarch/tcg/tlb_helper.c
> @@ -161,6 +161,7 @@ static void invalidate_tlb(CPULoongArchState *env, int index)
>           return;
>       }
>       invalidate_tlb_entry(env, index);
> +    tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
>   }

Why not move it all the way down into invalidate_elf_entry, after we've checked that E != 0?


r~

>   
>   static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb)
> @@ -340,7 +341,6 @@ void helper_tlbwr(CPULoongArchState *env)
>       old = env->tlb + index;
>       if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) {
>           invalidate_tlb(env, index);
> -        old->tlb_misc = FIELD_DP64(old->tlb_misc, TLB_MISC, E, 0);
>           return;
>       }
>   

Re: [PATCH v3 10/12] target/loongarch: Invalid tlb entry in invalidate_tlb()

[Bibo Mao]

On 2025/9/3 下午9:00, Richard Henderson wrote:
> On 9/3/25 10:48, Bibo Mao wrote:
>> Invalid tlb entry in function invalidate_tlb(), and its usage is
>> simple and easy to use.
>>
>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>> ---
>>   target/loongarch/tcg/tlb_helper.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/loongarch/tcg/tlb_helper.c 
>> b/target/loongarch/tcg/tlb_helper.c
>> index c074c956a2..ee40684a18 100644
>> --- a/target/loongarch/tcg/tlb_helper.c
>> +++ b/target/loongarch/tcg/tlb_helper.c
>> @@ -161,6 +161,7 @@ static void invalidate_tlb(CPULoongArchState *env, 
>> int index)
>>           return;
>>       }
>>       invalidate_tlb_entry(env, index);
>> +    tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
>>   }
> 
> Why not move it all the way down into invalidate_elf_entry, after we've 
> checked that E != 0?
Both are ok for me. invalidate_tlb_entry() is only called by 
invalidate_tlb().

Will do in this way.

Regards
Bibo Mao
> 
> 
> r~
> 
>>   static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb)
>> @@ -340,7 +341,6 @@ void helper_tlbwr(CPULoongArchState *env)
>>       old = env->tlb + index;
>>       if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) {
>>           invalidate_tlb(env, index);
>> -        old->tlb_misc = FIELD_DP64(old->tlb_misc, TLB_MISC, E, 0);
>>           return;
>>       }

[PATCH v3 11/12] target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid_or_g()

[Bibo Mao]

With function helper_invtlb_page_asid_or_g(), only one TLB entry in
LoongArch emulated TLB is invalidated. so with QEMU TLB, it is not
necessary to flush all QEMU TLB, only flush address range specified
LoongArch emulated TLB is ok. Here invalidate_tlb_entry() is called
so that only QEMU TLB entry with specified address range is flushed.

Signed-off-by: Bibo Mao <maobibo@loongson.cn
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/tcg/tlb_helper.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index ee40684a18..017c0d2f5b 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -560,7 +560,6 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
                                   target_ulong info, target_ulong addr)
 {
     int index, asid = info & 0x3ff;
-    LoongArchTLB *tlb;
     tlb_match func;
     bool ret;
 
@@ -570,9 +569,7 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
         return;
     }
 
-    tlb = &env->tlb[index];
-    tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
-    tlb_flush(env_cpu(env));
+    invalidate_tlb(env, index);
 }
 
 bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-- 
2.39.3

Re: [PATCH v3 11/12] target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid_or_g()

[Richard Henderson]

On 9/3/25 10:53, Bibo Mao wrote:
> With function helper_invtlb_page_asid_or_g(), only one TLB entry in
> LoongArch emulated TLB is invalidated. so with QEMU TLB, it is not
> necessary to flush all QEMU TLB, only flush address range specified
> LoongArch emulated TLB is ok. Here invalidate_tlb_entry() is called
> so that only QEMU TLB entry with specified address range is flushed.
> 
> Signed-off-by: Bibo Mao <maobibo@loongson.cn
> Signed-off-by: Bibo Mao<maobibo@loongson.cn>
> ---
>   target/loongarch/tcg/tlb_helper.c | 5 +----
>   1 file changed, 1 insertion(+), 4 deletions(-)

Double sign-off, both mis-formatted.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[PATCH v3 12/12] target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid()

[Bibo Mao]

With function helper_invtlb_page_asid(), only one TLB entry in
LoongArch emulated TLB is invalidated. so with QEMU TLB, it is not
necessary to flush all QEMU TLB, only flush address range specified
LoongArch emulated TLB is ok. Here invalidate_tlb_entry() is called
so that only QEMU TLB entry with specified address range is flushed.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/tcg/tlb_helper.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 017c0d2f5b..de0bbbb6b1 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -541,7 +541,6 @@ void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
                              target_ulong addr)
 {
     int index, asid = info & 0x3ff;
-    LoongArchTLB *tlb;
     tlb_match func;
     bool ret;
 
@@ -551,9 +550,7 @@ void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
         return;
     }
 
-    tlb = &env->tlb[index];
-    tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
-    tlb_flush(env_cpu(env));
+    invalidate_tlb(env, index);
 }
 
 void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
-- 
2.39.3

Re: [PATCH v3 12/12] target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid()

[Richard Henderson]

On 9/3/25 10:54, Bibo Mao wrote:
> With function helper_invtlb_page_asid(), only one TLB entry in
> LoongArch emulated TLB is invalidated. so with QEMU TLB, it is not
> necessary to flush all QEMU TLB, only flush address range specified
> LoongArch emulated TLB is ok. Here invalidate_tlb_entry() is called
> so that only QEMU TLB entry with specified address range is flushed.
> 
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>   target/loongarch/tcg/tlb_helper.c | 5 +----
>   1 file changed, 1 insertion(+), 4 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

> 
> diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
> index 017c0d2f5b..de0bbbb6b1 100644
> --- a/target/loongarch/tcg/tlb_helper.c
> +++ b/target/loongarch/tcg/tlb_helper.c
> @@ -541,7 +541,6 @@ void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
>                                target_ulong addr)
>   {
>       int index, asid = info & 0x3ff;
> -    LoongArchTLB *tlb;
>       tlb_match func;
>       bool ret;
>   
> @@ -551,9 +550,7 @@ void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
>           return;
>       }
>   
> -    tlb = &env->tlb[index];
> -    tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
> -    tlb_flush(env_cpu(env));
> +    invalidate_tlb(env, index);
>   }
>   
>   void helper_invtlb_page_asid_or_g(CPULoongArchState *env,