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([2a01:e0a:280:24f0:576b:abc6:6396:ed4a]) by smtp.gmail.com with ESMTPSA id n22-20020a7bcbd6000000b003f908ee3091sm6710817wmi.3.2023.06.19.10.36.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Jun 2023 10:36:46 -0700 (PDT) Message-ID: <682ff90d-3de5-7f12-25b0-edf252d20c95@redhat.com> Date: Mon, 19 Jun 2023 19:36:45 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH] target/arm: Restructure has_vfp_d32 test Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Mads Ynddal References: <20230619140216.402530-1-richard.henderson@linaro.org> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= In-Reply-To: <20230619140216.402530-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=clegoate@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/19/23 16:02, Richard Henderson wrote: > One cannot test for feature aa32_simd_r32 without first > testing if AArch32 mode is supported at all. This leads to > > qemu-system-aarch64: ARM CPUs must have both VFP-D32 and Neon or neither > > for Apple M1 cpus. The orangepi5 board I use didn't have that kind problem. > We already have a check for ARMv8-A never setting vfp-d32 true, > so restructure the code so that AArch64 avoids the test entirely. > > Reported-by: Mads Ynddal > Signed-off-by: Richard Henderson Reviewed-by: Cédric Le Goater Thanks for the fix, C. > --- > target/arm/cpu.c | 28 +++++++++++++++------------- > 1 file changed, 15 insertions(+), 13 deletions(-) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 353fc48567..706dbd37b1 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1402,25 +1402,27 @@ void arm_cpu_post_init(Object *obj) > * KVM does not currently allow us to lie to the guest about its > * ID/feature registers, so the guest always sees what the host has. > */ > - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) > - ? cpu_isar_feature(aa64_fp_simd, cpu) > - : cpu_isar_feature(aa32_vfp, cpu)) { > - cpu->has_vfp = true; > - if (!kvm_enabled()) { > - qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); > + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { > + if (cpu_isar_feature(aa64_fp_simd, cpu)) { > + cpu->has_vfp = true; > + cpu->has_vfp_d32 = true; > + if (tcg_enabled() || qtest_enabled()) { > + qdev_property_add_static(DEVICE(obj), > + &arm_cpu_has_vfp_property); > + } > } > - } > - > - if (cpu->has_vfp && cpu_isar_feature(aa32_simd_r32, cpu)) { > - cpu->has_vfp_d32 = true; > - if (!kvm_enabled()) { > + } else if (cpu_isar_feature(aa32_vfp, cpu)) { > + cpu->has_vfp = true; > + if (cpu_isar_feature(aa32_simd_r32, cpu)) { > + cpu->has_vfp_d32 = true; > /* > * The permitted values of the SIMDReg bits [3:0] on > * Armv8-A are either 0b0000 and 0b0010. On such CPUs, > * make sure that has_vfp_d32 can not be set to false. > */ > - if (!(arm_feature(&cpu->env, ARM_FEATURE_V8) && > - !arm_feature(&cpu->env, ARM_FEATURE_M))) { > + if ((tcg_enabled() || qtest_enabled()) > + && !(arm_feature(&cpu->env, ARM_FEATURE_V8) > + && !arm_feature(&cpu->env, ARM_FEATURE_M))) { > qdev_property_add_static(DEVICE(obj), > &arm_cpu_has_vfp_d32_property); > }