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References: <cover.1542321076.git.alistair.francis@wdc.com>
	<ccb312eb986d846b1b0aa0be062833e5ae1bb5f4.1542321076.git.alistair.francis@wdc.com>
From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <687076b9-a5ca-2821-3e24-8b08363f1b5c@linaro.org>
Date: Fri, 16 Nov 2018 18:10:12 +0100
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Subject: Re: [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct load
 and store instructions
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To: Alistair Francis <Alistair.Francis@wdc.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "alistair23@gmail.com" <alistair23@gmail.com>

On 11/15/18 11:36 PM, Alistair Francis wrote:
> +    tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);

Should avoid this when guest_base == 0, which happens fairly regularly for a
64-bit guest.

> +        /* Prefer to load from offset 0 first, but allow for overlap.  */
> +        if (TCG_TARGET_REG_BITS == 64) {
> +            tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
> +        } else {
> +            tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
> +            tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
> +        }

Comment sounds like two lines of code that's missing.

> +    const TCGMemOp bswap = opc & MO_BSWAP;
> +
> +    /* TODO: Handle byte swapping */

Should assert rather than emit bad code.

I do still plan to change tcg to allow backends to *not* handle byte swapping
if they don't want.  This will make the i386 and arm32 backends less icky.


r~