Re: [PATCH 2/2] target/riscv: The whole vector register move instructions depend on vsew

[Richard Henderson <richard.henderson@linaro.org>]

On 11/29/23 11:03, Max Chou wrote:
> The RISC-V v spec 16.6 section says that the whole vector register move
> instructions operate as if EEW=SEW. So it should depends on the vsew
> field of vtype register.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   target/riscv/insn_trans/trans_rvv.c.inc | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 114ad87397f..3871f0ea73d 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3643,8 +3643,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a)               \
>           QEMU_IS_ALIGNED(a->rs2, LEN)) {                                 \
>           uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN;                 \
>           if (s->vstart_eq_zero) {                                        \
> -            /* EEW = 8 */                                               \
> -            tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd),                  \
> +            tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),                \
>                                vreg_ofs(s, a->rs2), maxsz, maxsz);        \
>               mark_vs_dirty(s);                                           \
>           } else {                                                        \

This perhaps makes things clearer in the translator, but there is no difference in the tcg 
code generation end.  All logic operations (and, or, xor, mov...) ignore the element size.

Acked-by: Richard Henderson <richard.henderson@linaro.org>


r~