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[71.42.197.3]) by smtp.gmail.com with ESMTPSA id w4-20020a4a7644000000b0058d458b5420sm1975656ooe.47.2023.11.29.09.27.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Nov 2023 09:27:12 -0800 (PST) Message-ID: <68a73d87-bb90-413d-ba48-e4bd62c61bd9@linaro.org> Date: Wed, 29 Nov 2023 11:27:09 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] target/riscv: The whole vector register move instructions depend on vsew Content-Language: en-US To: Max Chou , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Junqiang Wang References: <20231129170400.21251-1-max.chou@sifive.com> <20231129170400.21251-3-max.chou@sifive.com> From: Richard Henderson In-Reply-To: <20231129170400.21251-3-max.chou@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c2b; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/29/23 11:03, Max Chou wrote: > The RISC-V v spec 16.6 section says that the whole vector register move > instructions operate as if EEW=SEW. So it should depends on the vsew > field of vtype register. > > Signed-off-by: Max Chou > --- > target/riscv/insn_trans/trans_rvv.c.inc | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 114ad87397f..3871f0ea73d 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -3643,8 +3643,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ > QEMU_IS_ALIGNED(a->rs2, LEN)) { \ > uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN; \ > if (s->vstart_eq_zero) { \ > - /* EEW = 8 */ \ > - tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \ > + tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), \ > vreg_ofs(s, a->rs2), maxsz, maxsz); \ > mark_vs_dirty(s); \ > } else { \ This perhaps makes things clearer in the translator, but there is no difference in the tcg code generation end. All logic operations (and, or, xor, mov...) ignore the element size. Acked-by: Richard Henderson r~