From: David Woodhouse <dwmw2@infradead.org>
To: qemu-devel@nongnu.org
Cc: "Michael S. Tsirkin" <mst@redhat.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>
Subject: Re: [PATCH] hw/timer/hpet: fix IRQ routing in legacy support mode
Date: Fri, 26 Jan 2024 12:10:03 +0000 [thread overview]
Message-ID: <68a78ef60be8f84540581b0eaf11daf0bd6a1248.camel@infradead.org> (raw)
In-Reply-To: <20231019000033.64684-1-dwmw2@infradead.org>
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On Thu, 2023-10-19 at 01:00 +0100, David Woodhouse wrote:
> From: David Woodhouse <dwmw@amazon.co.uk>
>
> The interrupt from timer 0 in legacy mode is supposed to go to IRQ 0 on
> the i8259 and IRQ 2 on the I/O APIC. The generic x86 GSI handling can't
> cope with IRQ numbers differing between the two chips (despite it also
> being the case for PCI INTx routing), so add a special case for the HPET.
>
> IRQ 2 isn't valid on the i8259; it's the cascade IRQ and would be
> interpreted as spurious interrupt on the secondary PIC. So we can fix
> up all attempts to deliver IRQ2, to actually deliver to IRQ0 on the PIC.
>
> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Ping?
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prev parent reply other threads:[~2024-01-26 12:10 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-19 0:00 [PATCH] hw/timer/hpet: fix IRQ routing in legacy support mode David Woodhouse
2024-01-26 12:10 ` David Woodhouse [this message]
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