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[213.30.8.110]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-443000ee99csm21776755e9.31.2025.05.16.07.43.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 May 2025 07:43:40 -0700 (PDT) Message-ID: <68cedad7-3f97-4040-9262-1039ddc6bb07@linaro.org> Date: Fri, 16 May 2025 15:43:39 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] hw/i386/amd_iommu: Fix device setup failure when PT is on. To: Sairaj Kodilkar , qemu-devel@nongnu.org Cc: mst@redhat.com, marcel.apfelbaum@gmail.com, pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, suravee.suthikulpanit@amd.com, alejandro.j.jimenez@oracle.com, joao.m.martins@oracle.com, Vasant Hegde References: <20250516100535.4980-1-sarunkod@amd.com> <20250516100535.4980-2-sarunkod@amd.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250516100535.4980-2-sarunkod@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 16/5/25 12:05, Sairaj Kodilkar wrote: > Commit c1f46999ef506 ("amd_iommu: Add support for pass though mode") > introduces the support for "pt" flag by enabling nodma memory when > "pt=off". This allowed VFIO devices to successfully register notifiers > by using nodma region. > > But, This also broke things when guest is booted with the iommu=nopt > because, devices bypass the IOMMU and use untranslated addresses (IOVA) to > perform DMA reads/writes to the nodma memory region, ultimately resulting in > a failure to setup the devices in the guest. > > Fix the above issue by always enabling the amdvi_dev_as->iommu memory region. > But this will once again cause VFIO devices to fail while registering the > notifiers with AMD IOMMU memory region. > > Fixes: c1f46999ef506 ("amd_iommu: Add support for pass though mode") > Signed-off-by: Sairaj Kodilkar > Reviewed-by: Vasant Hegde > --- > hw/i386/amd_iommu.c | 12 ++---------- > 1 file changed, 2 insertions(+), 10 deletions(-) > > diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c > index 5f9b95279997..df8ba5d39ada 100644 > --- a/hw/i386/amd_iommu.c > +++ b/hw/i386/amd_iommu.c > @@ -1426,7 +1426,6 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) > AMDVIState *s = opaque; > AMDVIAddressSpace **iommu_as, *amdvi_dev_as; > int bus_num = pci_bus_num(bus); > - X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); > > iommu_as = s->address_spaces[bus_num]; > > @@ -1486,15 +1485,8 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) > AMDVI_INT_ADDR_FIRST, > &amdvi_dev_as->iommu_ir, 1); > > - if (!x86_iommu->pt_supported) { > - memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, false); > - memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu), > - true); > - } else { > - memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu), > - false); > - memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, true); > - } > + memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, false); I have no clue about this device but wonder what is the usefulness of iommu_nodma now, isn't it dead code? > + memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu), true); > } > return &iommu_as[devfn]->as; > }