* [Qemu-devel] [PATCH v2 1/4] tricore: added some missing cpu instructions
2018-03-01 15:56 [Qemu-devel] [PATCH v2 0/4] tricore: added small features + fixed wrong masks David Brenken
@ 2018-03-01 15:56 ` David Brenken
2018-03-02 10:47 ` Bastian Koppelmann
2018-03-01 15:56 ` [Qemu-devel] [PATCH v2 2/4] tricore: added CORE_ID David Brenken
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: David Brenken @ 2018-03-01 15:56 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, David Brenken, Florian Artmeier, Georg Hofstetter
From: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: Florian Artmeier <florian.artmeier@efs-auto.de>
Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
---
target/tricore/translate.c | 27 +++++++++++++++++++++++++++
target/tricore/tricore-opcodes.h | 3 +++
2 files changed, 30 insertions(+)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 4e5b083..54de0dd 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -3389,10 +3389,18 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
offset);
break;
+ case OPC1_16_SBR_JEQ2:
+ gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
+ offset + 16);
+ break;
case OPC1_16_SBR_JNE:
gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
offset);
break;
+ case OPC1_16_SBR_JNE2:
+ gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
+ offset + 16);
+ break;
case OPC1_16_SBR_JNZ:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
break;
@@ -4121,6 +4129,16 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
gen_compute_branch(ctx, op1, 0, 0, const16, address);
break;
/* SBR-format */
+ case OPC1_16_SBR_JEQ2:
+ case OPC1_16_SBR_JNE2:
+ if (tricore_feature(env, TRICORE_FEATURE_16)) {
+ r1 = MASK_OP_SBR_S2(ctx->opcode);
+ address = MASK_OP_SBR_DISP4(ctx->opcode);
+ gen_compute_branch(ctx, op1, r1, 0, 0, address);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
case OPC1_16_SBR_JEQ:
case OPC1_16_SBR_JGEZ:
case OPC1_16_SBR_JGTZ:
@@ -6256,6 +6274,15 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
+ case OPC2_32_RR_MOVS_64:
+ if (tricore_feature(env, TRICORE_FEATURE_16)) {
+ CHECK_REG_PAIR(r3);
+ tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
+ tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
case OPC2_32_RR_NE:
tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index 08394b8..2c3baab 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -313,6 +313,7 @@ enum {
OPC1_16_SBC_JEQ = 0x1e,
OPC1_16_SBC_JEQ2 = 0x9e,
OPC1_16_SBR_JEQ = 0x3e,
+ OPC1_16_SBR_JEQ2 = 0xbe,
OPC1_16_SBR_JGEZ = 0xce,
OPC1_16_SBR_JGTZ = 0x4e,
OPC1_16_SR_JI = 0xdc,
@@ -321,6 +322,7 @@ enum {
OPC1_16_SBC_JNE = 0x5e,
OPC1_16_SBC_JNE2 = 0xde,
OPC1_16_SBR_JNE = 0x7e,
+ OPC1_16_SBR_JNE2 = 0xfe,
OPC1_16_SB_JNZ = 0xee,
OPC1_16_SBR_JNZ = 0xf6,
OPC1_16_SBR_JNZ_A = 0x7c,
@@ -1064,6 +1066,7 @@ enum {
OPC2_32_RR_MIN_H = 0x78,
OPC2_32_RR_MIN_HU = 0x79,
OPC2_32_RR_MOV = 0x1f,
+ OPC2_32_RR_MOVS_64 = 0x80,
OPC2_32_RR_MOV_64 = 0x81,
OPC2_32_RR_NE = 0x11,
OPC2_32_RR_OR_EQ = 0x27,
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH v2 1/4] tricore: added some missing cpu instructions
2018-03-01 15:56 ` [Qemu-devel] [PATCH v2 1/4] tricore: added some missing cpu instructions David Brenken
@ 2018-03-02 10:47 ` Bastian Koppelmann
0 siblings, 0 replies; 9+ messages in thread
From: Bastian Koppelmann @ 2018-03-02 10:47 UTC (permalink / raw)
To: David Brenken, qemu-devel
Cc: Florian Artmeier, David Brenken, Georg Hofstetter
On 03/01/2018 04:56 PM, David Brenken wrote:
> From: David Brenken <david.brenken@efs-auto.de>
>
> Signed-off-by: David Brenken <david.brenken@efs-auto.de>
> Signed-off-by: Florian Artmeier <florian.artmeier@efs-auto.de>
> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
> ---
> target/tricore/translate.c | 27 +++++++++++++++++++++++++++
> target/tricore/tricore-opcodes.h | 3 +++
> 2 files changed, 30 insertions(+)
A more descriptive commit message would be nice. Which instructions have
been added?
Cheers,
Bastian
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v2 2/4] tricore: added CORE_ID
2018-03-01 15:56 [Qemu-devel] [PATCH v2 0/4] tricore: added small features + fixed wrong masks David Brenken
2018-03-01 15:56 ` [Qemu-devel] [PATCH v2 1/4] tricore: added some missing cpu instructions David Brenken
@ 2018-03-01 15:56 ` David Brenken
2018-03-02 10:49 ` Bastian Koppelmann
2018-03-01 15:56 ` [Qemu-devel] [PATCH v2 3/4] tricore: renamed masking of IE David Brenken
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: David Brenken @ 2018-03-01 15:56 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, David Brenken, Florian Artmeier, Georg Hofstetter
From: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: Florian Artmeier <florian.artmeier@efs-auto.de>
Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
---
target/tricore/cpu.h | 1 +
target/tricore/csfr.def | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index f41d2ce..c295763 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -59,6 +59,7 @@ struct CPUTriCoreState {
uint32_t PC;
uint32_t SYSCON;
uint32_t CPU_ID;
+ uint32_t CORE_ID;
uint32_t BIV;
uint32_t BTV;
uint32_t ISP;
diff --git a/target/tricore/csfr.def b/target/tricore/csfr.def
index 05c45dd..ff004cb 100644
--- a/target/tricore/csfr.def
+++ b/target/tricore/csfr.def
@@ -10,6 +10,7 @@ A(0xfe00, PCXI, TRICORE_FEATURE_13)
A(0xfe08, PC, TRICORE_FEATURE_13)
A(0xfe14, SYSCON, TRICORE_FEATURE_13)
R(0xfe18, CPU_ID, TRICORE_FEATURE_13)
+R(0xfe1c, CORE_ID, TRICORE_FEATURE_161)
E(0xfe20, BIV, TRICORE_FEATURE_13)
E(0xfe24, BTV, TRICORE_FEATURE_13)
E(0xfe28, ISP, TRICORE_FEATURE_13)
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH v2 2/4] tricore: added CORE_ID
2018-03-01 15:56 ` [Qemu-devel] [PATCH v2 2/4] tricore: added CORE_ID David Brenken
@ 2018-03-02 10:49 ` Bastian Koppelmann
0 siblings, 0 replies; 9+ messages in thread
From: Bastian Koppelmann @ 2018-03-02 10:49 UTC (permalink / raw)
To: David Brenken, qemu-devel
Cc: Florian Artmeier, David Brenken, Georg Hofstetter
On 03/01/2018 04:56 PM, David Brenken wrote:
> From: David Brenken <david.brenken@efs-auto.de>
>
> Signed-off-by: David Brenken <david.brenken@efs-auto.de>
> Signed-off-by: Florian Artmeier <florian.artmeier@efs-auto.de>
> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
> ---
> target/tricore/cpu.h | 1 +
> target/tricore/csfr.def | 1 +
> 2 files changed, 2 insertions(+)
>
I gave you a Reviewed-by for this patch. If you get one of those please
add it to the next patchset's commit message.
Cheers,
Bastian
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v2 3/4] tricore: renamed masking of IE
2018-03-01 15:56 [Qemu-devel] [PATCH v2 0/4] tricore: added small features + fixed wrong masks David Brenken
2018-03-01 15:56 ` [Qemu-devel] [PATCH v2 1/4] tricore: added some missing cpu instructions David Brenken
2018-03-01 15:56 ` [Qemu-devel] [PATCH v2 2/4] tricore: added CORE_ID David Brenken
@ 2018-03-01 15:56 ` David Brenken
2018-03-02 10:48 ` Bastian Koppelmann
2018-03-01 15:56 ` [Qemu-devel] [PATCH v2 4/4] tricore: renamed masking of PIE David Brenken
2018-03-02 10:41 ` [Qemu-devel] [PATCH v2 0/4] tricore: added small features + fixed wrong masks Bastian Koppelmann
4 siblings, 1 reply; 9+ messages in thread
From: David Brenken @ 2018-03-01 15:56 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, David Brenken, Florian Artmeier, Georg Hofstetter
From: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: Florian Artmeier <florian.artmeier@efs-auto.de>
Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
---
target/tricore/cpu.h | 3 ++-
target/tricore/op_helper.c | 17 +++++++++--------
target/tricore/translate.c | 4 ++--
3 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index c295763..a98b6f2 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -257,7 +257,8 @@ void tricore_cpu_dump_state(CPUState *cpu, FILE *f,
#define MASK_CPUID_REV 0x000000ff
#define MASK_ICR_PIPN 0x00ff0000
-#define MASK_ICR_IE 0x00000100
+#define MASK_ICR_IE_1_3 0x00000100
+#define MASK_ICR_IE_1_6 0x00008000
#define MASK_ICR_CCPN 0x000000ff
#define MASK_FCX_FCXS 0x000f0000
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 098f217..475b6ce 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -85,7 +85,7 @@ raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int tin,
/* PCXI.PIE = ICR.IE */
env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
- ((env->ICR & MASK_ICR_IE) << 15));
+ ((env->ICR & MASK_ICR_IE_1_3) << 15));
/* PCXI.PCPN = ICR.CCPN */
env->PCXI = (env->PCXI & 0xffffff) +
((env->ICR & MASK_ICR_CCPN) << 24);
@@ -2465,7 +2465,7 @@ void helper_call(CPUTriCoreState *env, uint32_t next_pc)
((env->ICR & MASK_ICR_CCPN) << 24);
/* PCXI.PIE = ICR.IE; */
env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
- ((env->ICR & MASK_ICR_IE) << 15));
+ ((env->ICR & MASK_ICR_IE_1_3) << 15));
/* PCXI.UL = 1; */
env->PCXI |= MASK_PCXI_UL;
@@ -2563,7 +2563,7 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const9)
((env->ICR & MASK_ICR_CCPN) << 24);
/* PCXI.PIE = ICR.IE */
env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
- ((env->ICR & MASK_ICR_IE) << 15));
+ ((env->ICR & MASK_ICR_IE_1_3) << 15));
/* PCXI.UL = 0 */
env->PCXI &= ~(MASK_PCXI_UL);
/* PCXI[19: 0] = FCX[19: 0] */
@@ -2571,7 +2571,7 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const9)
/* FXC[19: 0] = new_FCX[19: 0] */
env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff);
/* ICR.IE = 1 */
- env->ICR |= MASK_ICR_IE;
+ env->ICR |= MASK_ICR_IE_1_3;
env->ICR |= const9; /* ICR.CCPN = const9[7: 0];*/
@@ -2603,7 +2603,8 @@ void helper_rfe(CPUTriCoreState *env)
}
env->PC = env->gpr_a[11] & ~0x1;
/* ICR.IE = PCXI.PIE; */
- env->ICR = (env->ICR & ~MASK_ICR_IE) + ((env->PCXI & MASK_PCXI_PIE) >> 15);
+ env->ICR = (env->ICR & ~MASK_ICR_IE_1_3)
+ + ((env->PCXI & MASK_PCXI_PIE) >> 15);
/* ICR.CCPN = PCXI.PCPN; */
env->ICR = (env->ICR & ~MASK_ICR_CCPN) +
((env->PCXI & MASK_PCXI_PCPN) >> 24);
@@ -2627,7 +2628,7 @@ void helper_rfm(CPUTriCoreState *env)
{
env->PC = (env->gpr_a[11] & ~0x1);
/* ICR.IE = PCXI.PIE; */
- env->ICR = (env->ICR & ~MASK_ICR_IE) |
+ env->ICR = (env->ICR & ~MASK_ICR_IE_1_3) |
((env->PCXI & MASK_PCXI_PIE) >> 15);
/* ICR.CCPN = PCXI.PCPN; */
env->ICR = (env->ICR & ~MASK_ICR_CCPN) |
@@ -2694,7 +2695,7 @@ void helper_svlcx(CPUTriCoreState *env)
((env->ICR & MASK_ICR_CCPN) << 24);
/* PCXI.PIE = ICR.IE; */
env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
- ((env->ICR & MASK_ICR_IE) << 15));
+ ((env->ICR & MASK_ICR_IE_1_3) << 15));
/* PCXI.UL = 0; */
env->PCXI &= ~MASK_PCXI_UL;
@@ -2737,7 +2738,7 @@ void helper_svucx(CPUTriCoreState *env)
((env->ICR & MASK_ICR_CCPN) << 24);
/* PCXI.PIE = ICR.IE; */
env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
- ((env->ICR & MASK_ICR_IE) << 15));
+ ((env->ICR & MASK_ICR_IE_1_3) << 15));
/* PCXI.UL = 1; */
env->PCXI |= MASK_PCXI_UL;
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 54de0dd..aef0d9c 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8379,12 +8379,12 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx)
/* raise EXCP_DEBUG */
break;
case OPC2_32_SYS_DISABLE:
- tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE);
+ tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3);
break;
case OPC2_32_SYS_DSYNC:
break;
case OPC2_32_SYS_ENABLE:
- tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE);
+ tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE_1_3);
break;
case OPC2_32_SYS_ISYNC:
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH v2 3/4] tricore: renamed masking of IE
2018-03-01 15:56 ` [Qemu-devel] [PATCH v2 3/4] tricore: renamed masking of IE David Brenken
@ 2018-03-02 10:48 ` Bastian Koppelmann
0 siblings, 0 replies; 9+ messages in thread
From: Bastian Koppelmann @ 2018-03-02 10:48 UTC (permalink / raw)
To: David Brenken, qemu-devel
Cc: Florian Artmeier, David Brenken, Georg Hofstetter
On 03/01/2018 04:56 PM, David Brenken wrote:
> From: David Brenken <david.brenken@efs-auto.de>
>
> Signed-off-by: David Brenken <david.brenken@efs-auto.de>
> Signed-off-by: Florian Artmeier <florian.artmeier@efs-auto.de>
> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
> ---
> target/tricore/cpu.h | 3 ++-
> target/tricore/op_helper.c | 17 +++++++++--------
> target/tricore/translate.c | 4 ++--
> 3 files changed, 13 insertions(+), 11 deletions(-)
>
The commit message should also reflect why we made this change, i.e.
architecture differences.
Cheers,
Bastian
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v2 4/4] tricore: renamed masking of PIE
2018-03-01 15:56 [Qemu-devel] [PATCH v2 0/4] tricore: added small features + fixed wrong masks David Brenken
` (2 preceding siblings ...)
2018-03-01 15:56 ` [Qemu-devel] [PATCH v2 3/4] tricore: renamed masking of IE David Brenken
@ 2018-03-01 15:56 ` David Brenken
2018-03-02 10:41 ` [Qemu-devel] [PATCH v2 0/4] tricore: added small features + fixed wrong masks Bastian Koppelmann
4 siblings, 0 replies; 9+ messages in thread
From: David Brenken @ 2018-03-01 15:56 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, David Brenken, Florian Artmeier, Georg Hofstetter
From: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: Florian Artmeier <florian.artmeier@efs-auto.de>
Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
---
target/tricore/cpu.h | 3 ++-
target/tricore/op_helper.c | 16 ++++++++--------
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index a98b6f2..defab5e 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -230,7 +230,8 @@ void tricore_cpu_dump_state(CPUState *cpu, FILE *f,
#define MASK_PCXI_PCPN 0xff000000
-#define MASK_PCXI_PIE 0x00800000
+#define MASK_PCXI_PIE_1_3 0x00800000
+#define MASK_PCXI_PIE_1_6 0x00200000
#define MASK_PCXI_UL 0x00400000
#define MASK_PCXI_PCXS 0x000f0000
#define MASK_PCXI_PCXO 0x0000ffff
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 475b6ce..16955f2 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -84,7 +84,7 @@ raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int tin,
ICR.IE and ICR.CCPN are saved */
/* PCXI.PIE = ICR.IE */
- env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
+ env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) +
((env->ICR & MASK_ICR_IE_1_3) << 15));
/* PCXI.PCPN = ICR.CCPN */
env->PCXI = (env->PCXI & 0xffffff) +
@@ -2464,7 +2464,7 @@ void helper_call(CPUTriCoreState *env, uint32_t next_pc)
env->PCXI = (env->PCXI & 0xffffff) +
((env->ICR & MASK_ICR_CCPN) << 24);
/* PCXI.PIE = ICR.IE; */
- env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
+ env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) +
((env->ICR & MASK_ICR_IE_1_3) << 15));
/* PCXI.UL = 1; */
env->PCXI |= MASK_PCXI_UL;
@@ -2562,7 +2562,7 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const9)
env->PCXI = (env->PCXI & 0xffffff) +
((env->ICR & MASK_ICR_CCPN) << 24);
/* PCXI.PIE = ICR.IE */
- env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
+ env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) +
((env->ICR & MASK_ICR_IE_1_3) << 15));
/* PCXI.UL = 0 */
env->PCXI &= ~(MASK_PCXI_UL);
@@ -2604,7 +2604,7 @@ void helper_rfe(CPUTriCoreState *env)
env->PC = env->gpr_a[11] & ~0x1;
/* ICR.IE = PCXI.PIE; */
env->ICR = (env->ICR & ~MASK_ICR_IE_1_3)
- + ((env->PCXI & MASK_PCXI_PIE) >> 15);
+ + ((env->PCXI & MASK_PCXI_PIE_1_3) >> 15);
/* ICR.CCPN = PCXI.PCPN; */
env->ICR = (env->ICR & ~MASK_ICR_CCPN) +
((env->PCXI & MASK_PCXI_PCPN) >> 24);
@@ -2628,8 +2628,8 @@ void helper_rfm(CPUTriCoreState *env)
{
env->PC = (env->gpr_a[11] & ~0x1);
/* ICR.IE = PCXI.PIE; */
- env->ICR = (env->ICR & ~MASK_ICR_IE_1_3) |
- ((env->PCXI & MASK_PCXI_PIE) >> 15);
+ env->ICR = (env->ICR & ~MASK_ICR_IE_1_3)
+ | ((env->PCXI & MASK_PCXI_PIE_1_3) >> 15);
/* ICR.CCPN = PCXI.PCPN; */
env->ICR = (env->ICR & ~MASK_ICR_CCPN) |
((env->PCXI & MASK_PCXI_PCPN) >> 24);
@@ -2694,7 +2694,7 @@ void helper_svlcx(CPUTriCoreState *env)
env->PCXI = (env->PCXI & 0xffffff) +
((env->ICR & MASK_ICR_CCPN) << 24);
/* PCXI.PIE = ICR.IE; */
- env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
+ env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) +
((env->ICR & MASK_ICR_IE_1_3) << 15));
/* PCXI.UL = 0; */
env->PCXI &= ~MASK_PCXI_UL;
@@ -2737,7 +2737,7 @@ void helper_svucx(CPUTriCoreState *env)
env->PCXI = (env->PCXI & 0xffffff) +
((env->ICR & MASK_ICR_CCPN) << 24);
/* PCXI.PIE = ICR.IE; */
- env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
+ env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) +
((env->ICR & MASK_ICR_IE_1_3) << 15));
/* PCXI.UL = 1; */
env->PCXI |= MASK_PCXI_UL;
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH v2 0/4] tricore: added small features + fixed wrong masks
2018-03-01 15:56 [Qemu-devel] [PATCH v2 0/4] tricore: added small features + fixed wrong masks David Brenken
` (3 preceding siblings ...)
2018-03-01 15:56 ` [Qemu-devel] [PATCH v2 4/4] tricore: renamed masking of PIE David Brenken
@ 2018-03-02 10:41 ` Bastian Koppelmann
4 siblings, 0 replies; 9+ messages in thread
From: Bastian Koppelmann @ 2018-03-02 10:41 UTC (permalink / raw)
To: David Brenken, qemu-devel; +Cc: David Brenken
Hi David,
On 03/01/2018 04:56 PM, David Brenken wrote:
> From: David Brenken <david.brenken@efs-auto.de>
>
> Hi Bastian,
>
> thank you for your feedback and sorry for the late reply.
>
> Changes from v1:
> * Removed OPC1_16_SB_JNE instruction.
> * Added CPU feature checks to new instructions.
> * Renamed ICR.IE and PCXI.PIE masks and added corresponding TC 1.6 masks.
> * Squashed patch 4/5 and 5/5.
This looks good to me. I'll apply it to my tricore-next branch and I
will send a pull request for upstream soon. I still have some minor nit
picks (see email inlines). However, you don't have to respin -- they are
minor and I will fix them before applying, due to softfreeze being right
around the corner.
>
> From the previous implementation I was unable to see that there are architecture differences between TriCore version 1.3 and version 1.6 (e.g. the masking of ICR.IE and PCXI.PIE).
> I did not correct the situation technically but with this patch set one will be able to recognize the differences.
>
> My plan is to correct this issue in a future patch series. Inspecting the code I recognized that changing only the bit mask of ICR.IE and PCXI.PIE depending on the processor version would not solve the problem since also the shifting often used in that context depends on the architecure (e.g. in op_helper.c /* PCXI.PIE = ICR.IE */).
> Therefore I would create functions for the storing and restoring of ICR.IE. These functions would have different implementations for the given processor versions.
Of course. My suggestion was just in the interest of this patch series.
I'd be happy to review your proper solution.
Cheers,
Bastian
^ permalink raw reply [flat|nested] 9+ messages in thread