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([2602:47:d48c:8101:c606:9489:98df:6a3b]) by smtp.gmail.com with ESMTPSA id q2-20020a170902eb8200b001898ca438fcsm1813575plg.282.2022.12.16.08.29.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Dec 2022 08:29:41 -0800 (PST) Message-ID: <6900a10d-8128-72cd-c827-715e73473e3e@linaro.org> Date: Fri, 16 Dec 2022 08:29:39 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH] target/arm: Don't set EXC_RETURN.ES if Security Extension not present Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Igor Kotrasinski References: <20221216152410.1185369-1-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20221216152410.1185369-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/16/22 07:24, Peter Maydell wrote: > In v7m_exception_taken(), for v8M we set the EXC_RETURN.ES bit if > either the exception targets Secure or if the CPU doesn't implement > the Security Extension. This is incorrect: the v8M Arm ARM specifies > that the ES bit should be RES0 if the Security Extension is not > implemented, and the pseudocode agrees. > > Remove the incorrect condition, so that we leave the ES bit 0 > if the Security Extension isn't implemented. > > This doesn't have any guest-visible effects for our current set of > emulated CPUs, because all our v8M CPUs implement the Security > Extension; but it's worth fixing in case we add a v8M CPU without > the extension in future. > > Reported-by: Igor Kotrasinski > Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson r~ > --- > target/arm/m_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c > index 355cd4d60a7..2b55e90ea9d 100644 > --- a/target/arm/m_helper.c > +++ b/target/arm/m_helper.c > @@ -895,7 +895,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, > } > > lr &= ~R_V7M_EXCRET_ES_MASK; > - if (targets_secure || !arm_feature(env, ARM_FEATURE_M_SECURITY)) { > + if (targets_secure) { > lr |= R_V7M_EXCRET_ES_MASK; > } > lr &= ~R_V7M_EXCRET_SPSEL_MASK;