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([2804:7f0:b400:bb79:4bdf:de43:1f6c:1151]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-714342732b5sm8727852b3a.92.2024.08.27.05.42.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Aug 2024 05:42:05 -0700 (PDT) Subject: Re: [PATCH v3 4/4] tests/tcg/aarch64: Extend MTE gdbstub tests to system mode To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org, alex.bennee@linaro.org, richard.henderson@linaro.org Cc: peter.maydell@linaro.org References: <20240825145208.46774-1-gustavo.romero@linaro.org> <20240825145208.46774-5-gustavo.romero@linaro.org> <64200fe4-b824-4903-b5f5-fc48c9e00945@linaro.org> From: Gustavo Romero Message-ID: <69229d7b-15d5-feda-ee4b-1c48992297f3@linaro.org> Date: Tue, 27 Aug 2024 09:42:02 -0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <64200fe4-b824-4903-b5f5-fc48c9e00945@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=gustavo.romero@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.192, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Phil! On 8/26/24 3:10 AM, Philippe Mathieu-Daudé wrote: > Hi Gustavo, > > On 25/8/24 16:52, Gustavo Romero wrote: >> Extend MTE gdbstub tests to also run in system mode (share tests between >> user mode and system mode). The tests will only run if a version of GDB >> that supports MTE on baremetal is available in the test environment and >> if available compiler supports the 'memtag' flag >> (-march=armv8.5-a+memtag). >> >> For the tests running in system mode, a page that supports MTE ops. is >> necessary. Therefore, an MTE-enabled page is made available (mapped) in >> the third 2 MB chunk of the second 1 GB space in the flat mapping set in >> boot.S. A new binary, mte.S, is also introduced for the tests. It links >> against boot.S and is executed by QEMU in system mode. >> >> Signed-off-by: Gustavo Romero >> --- >>   configure                                 |   5 + >>   tests/tcg/aarch64/Makefile.softmmu-target |  49 +++++++++- >>   tests/tcg/aarch64/Makefile.target         |   3 +- >>   tests/tcg/aarch64/gdbstub/test-mte.py     |  71 +++++++++----- >>   tests/tcg/aarch64/system/boot.S           |  11 +++ >>   tests/tcg/aarch64/system/kernel.ld        |   7 ++ >>   tests/tcg/aarch64/system/mte.S            | 109 ++++++++++++++++++++++ >>   7 files changed, 227 insertions(+), 28 deletions(-) >>   create mode 100644 tests/tcg/aarch64/system/mte.S > > >> diff --git a/tests/tcg/aarch64/system/kernel.ld b/tests/tcg/aarch64/system/kernel.ld >> index 7b3a76dcbf..46f1092522 100644 >> --- a/tests/tcg/aarch64/system/kernel.ld >> +++ b/tests/tcg/aarch64/system/kernel.ld >> @@ -18,6 +18,13 @@ SECTIONS >>       .bss : { >>           *(.bss) >>       } >> +    /* >> +     * Align the MTE page to the next 2mb boundary (i.e., the third 2mb chunk >> +     * starting from 1gb) by setting the address for symbol 'mte_page', which is >> +     * used in boot.S to setup the PTE and in the mte.S test as the address that >> +     * the MTE instructions operate on. >> +     */ >> +    mte_page = ALIGN(1 << 22); > > Comment says 2MiB but you use 4MiB. > Matter of taste, 2MiB is easier to review as: > >       mte_page = ALIGN(2 << 20); > This is incorrect. Aligning here at 2MiB will clash with r/w data section. I tried to clarify it when I wrote "[...] third 2mb chunk starting from 1gb". The memory layout so is: 0 ---- 1GiB range: avoid/skipped 1GiB ---- 1GiB+2MiB (1st 2MiB chunk): text 1GiB+2MiB ---- 1GiB+4MiB (2nd 2MiB chunk): data 1GiB+4MIB ---- 1GiB+8MiB (3rd 2MiB chunk): MTE-enabled page ALIGN implicitly uses "." (current position), so we're defining consecutive sections here starting from 1GiB. All the other parts of the code uses the 1 << n form, which I prefer, specially when reading asm code, so I prefer 1 << 22 instead of 4 << 20. But apparently my comment failed miserable to explain the situation here, so I'm happy to change the wording to make it clearer if you have any suggestion. Cheers, Gustavo >>       /DISCARD/ : { >>           *(.ARM.attributes) >>       } >