[PULL 0/1] riscv-to-apply queue

[PULL 0/1] riscv-to-apply queue

[Alistair Francis]

The following changes since commit 2eefd4fcec4b8fe41ceee2a8f00cdec1fe81b75c:

  Merge tag 'pull-maintainer-9.1-rc3-160824-1' of https://gitlab.com/stsquad/qemu into staging (2024-08-17 16:46:45 +1000)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240819-1

for you to fetch changes up to 6df664f87c738788891f3bda701e63e23a0dbbc2:

  Revert "hw/riscv/virt.c: imsics DT: add '#msi-cells'" (2024-08-19 14:34:49 +1000)

----------------------------------------------------------------
RISC-V PR for 9.1

This reverts a commit adding `#msi-cells=<0>` to the virt machine
as that commit results in PCI devices unable to us MSIs. Even though
it's a kernel bug, we don't want to break existing users.

* Revert adding #msi-cells to virt machine

----------------------------------------------------------------
Andrew Jones (1):
      Revert "hw/riscv/virt.c: imsics DT: add '#msi-cells'"

 hw/riscv/virt.c | 1 -
 1 file changed, 1 deletion(-)

[PULL 1/1] Revert "hw/riscv/virt.c: imsics DT: add '#msi-cells'"

[Alistair Francis]

From: Andrew Jones <ajones@ventanamicro.com>

This reverts commit f42cdf2ea5b3a1dc369792d7acbf9cd3e5c90815.

Linux does not properly handle '#msi-cells=<0>' when searching for
MSI controllers for PCI devices which results in the devices being
unable to use MSIs. A patch for Linux has been sent[1] but until it,
or something like it, is merged and in distro kernels we should stop
adding the property. It's harmless to stop adding it since the
absence of the property and a value of zero for the property mean
the same thing according to the DT binding definition.

Link: https://lore.kernel.org/all/20240816124957.130017-2-ajones@ventanamicro.com/ # 1
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240816160743.220374-5-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 9981e0f6c9..cef41c150a 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -552,7 +552,6 @@ static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr,
                           FDT_IMSIC_INT_CELLS);
     qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0);
     qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0);
-    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#msi-cells", 0);
     qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
                      imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
     qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
-- 
2.46.0

Re: [PULL 0/1] riscv-to-apply queue

[Richard Henderson]

On 8/19/24 14:43, Alistair Francis wrote:
> The following changes since commit 2eefd4fcec4b8fe41ceee2a8f00cdec1fe81b75c:
> 
>    Merge tag 'pull-maintainer-9.1-rc3-160824-1' ofhttps://gitlab.com/stsquad/qemu into staging (2024-08-17 16:46:45 +1000)
> 
> are available in the Git repository at:
> 
>    https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240819-1
> 
> for you to fetch changes up to 6df664f87c738788891f3bda701e63e23a0dbbc2:
> 
>    Revert "hw/riscv/virt.c: imsics DT: add '#msi-cells'" (2024-08-19 14:34:49 +1000)
> 
> ----------------------------------------------------------------
> RISC-V PR for 9.1
> 
> This reverts a commit adding `#msi-cells=<0>` to the virt machine
> as that commit results in PCI devices unable to us MSIs. Even though
> it's a kernel bug, we don't want to break existing users.
> 
> * Revert adding #msi-cells to virt machine

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate.

r~

[PULL 0/1] riscv-to-apply queue

[Alistair Francis]

The following changes since commit 53f3a13ac1069975ad47cf8bd05cc96b4ac09962:

  Merge tag 'pull-tcg-20250403' of https://gitlab.com/rth7680/qemu into staging (2025-04-04 10:23:17 -0400)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20250407-1

for you to fetch changes up to d31d37fded414959713678d2e9e6bc1afab5f376:

  docs: deprecate RISC-V default machine option (2025-04-07 10:12:40 +1000)

----------------------------------------------------------------
Sixth RISC-V PR for 10.0

* Deprecate the default RISC-V machine

----------------------------------------------------------------
Daniel Henrique Barboza (1):
      docs: deprecate RISC-V default machine option

 docs/about/deprecated.rst | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

Re: [PULL 0/1] riscv-to-apply queue

[Stefan Hajnoczi]

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Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes.

[-- Attachment #2: signature.asc --]
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[PULL 0/1] riscv-to-apply queue

[Alistair Francis]

The following changes since commit d1181d29370a4318a9f11ea92065bea6bb159f83:

  Merge tag 'pull-nbd-2023-07-19' of https://repo.or.cz/qemu/ericb into staging (2023-07-20 09:54:07 +0100)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230723-3

for you to fetch changes up to dcaaf2bf9bfd2c664dbeff0069fcab3d75c924d3:

  roms/opensbi: Upgrade from v1.3 to v1.3.1 (2023-07-23 19:32:02 +1000)

----------------------------------------------------------------
Fifth RISC-V PR for 8.1

* roms/opensbi: Upgrade from v1.3 to v1.3.1

----------------------------------------------------------------
Bin Meng (1):
      roms/opensbi: Upgrade from v1.3 to v1.3.1

 pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 135344 -> 135376 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 138304 -> 138368 bytes
 roms/opensbi                                   |   2 +-
 3 files changed, 1 insertion(+), 1 deletion(-)

Re: [PULL 0/1] riscv-to-apply queue

[Peter Maydell]

On Sun, 23 Jul 2023 at 10:35, Alistair Francis <alistair23@gmail.com> wrote:
>
> The following changes since commit d1181d29370a4318a9f11ea92065bea6bb159f83:
>
>   Merge tag 'pull-nbd-2023-07-19' of https://repo.or.cz/qemu/ericb into staging (2023-07-20 09:54:07 +0100)
>
> are available in the Git repository at:
>
>   https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230723-3
>
> for you to fetch changes up to dcaaf2bf9bfd2c664dbeff0069fcab3d75c924d3:
>
>   roms/opensbi: Upgrade from v1.3 to v1.3.1 (2023-07-23 19:32:02 +1000)
>
> ----------------------------------------------------------------
> Fifth RISC-V PR for 8.1
>
> * roms/opensbi: Upgrade from v1.3 to v1.3.1
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.1
for any user-visible changes.

-- PMM

[PULL 0/1] riscv-to-apply queue

[Alistair Francis]

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 0e0c2cf6de0bc6538840837c63b25817cd417347:

  Merge tag 'pull-target-arm-20220801' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-08-01 12:00:08 -0700)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220802

for you to fetch changes up to 1eaa63429a9944265c92efdb94c02fabb231f564:

  linux-user/riscv: Align signal frame to 16 bytes (2022-08-02 08:56:49 +1000)

----------------------------------------------------------------
Seventh RISC-V PR for QEMU 7.1

This is a second PR to go in for RC1. It fixes a bug we have had
for awhile, but it's a simple fix so let's pull it in for RC1.

* linux-user/riscv: Align signal frame to 16 bytes

----------------------------------------------------------------
Richard Henderson (1):
      linux-user/riscv: Align signal frame to 16 bytes

 linux-user/riscv/signal.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

Re: [PULL 0/1] riscv-to-apply queue

[Richard Henderson]

On 8/1/22 16:02, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> The following changes since commit 0e0c2cf6de0bc6538840837c63b25817cd417347:
> 
>    Merge tag 'pull-target-arm-20220801' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-08-01 12:00:08 -0700)
> 
> are available in the Git repository at:
> 
>    git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220802
> 
> for you to fetch changes up to 1eaa63429a9944265c92efdb94c02fabb231f564:
> 
>    linux-user/riscv: Align signal frame to 16 bytes (2022-08-02 08:56:49 +1000)
> 
> ----------------------------------------------------------------
> Seventh RISC-V PR for QEMU 7.1
> 
> This is a second PR to go in for RC1. It fixes a bug we have had
> for awhile, but it's a simple fix so let's pull it in for RC1.
> 
> * linux-user/riscv: Align signal frame to 16 bytes

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate.


r~


> 
> ----------------------------------------------------------------
> Richard Henderson (1):
>        linux-user/riscv: Align signal frame to 16 bytes
> 
>   linux-user/riscv/signal.c | 4 +---
>   1 file changed, 1 insertion(+), 3 deletions(-)
>