From: Richard Henderson <richard.henderson@linaro.org>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>, qemu-devel@nongnu.org
Cc: pbonzini@redhat.com, Brian Cain <bcain@quicinc.com>
Subject: Re: [PATCH v2 0/2] tcg: Streamline vector load/store
Date: Tue, 17 Oct 2023 06:38:01 -0700 [thread overview]
Message-ID: <69691ad3-e4cc-43c7-9f81-b00988ebff76@linaro.org> (raw)
In-Reply-To: <2ccd41e7-bc4a-9223-7f56-04493e0357d4@linaro.org>
On 10/17/23 04:52, Philippe Mathieu-Daudé wrote:
> On 13/10/23 19:51, Richard Henderson wrote:
>> We have tcg_gen_qemu_{ld,st}_i128, which can be used to implement
>> load/store of vectors to guest memory. But at present we have to
>> split into, or concatenated from, two i64 to reference the guest
>> vector register backing store within env.
>>
>> Provide tcg_gen_{ld,st}_i128, which can avoid the trip through i64.
>>
>> This does require that the target store i128 in host byte ordering,
>> which is true of i386 (and some other backends) but not arm or s390x.
>> There is definitely further cleanup possible.
>
> Is hexagon gen_vreg_load() candidate?
Yes.
r~
prev parent reply other threads:[~2023-10-17 13:38 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-13 17:51 [PATCH v2 0/2] tcg: Streamline vector load/store Richard Henderson
2023-10-13 17:51 ` [PATCH v2 1/2] tcg: Add tcg_gen_{ld,st}_i128 Richard Henderson
2023-10-17 11:48 ` Philippe Mathieu-Daudé
2023-10-18 1:19 ` gaosong
2023-10-18 5:03 ` Philippe Mathieu-Daudé
2023-10-13 17:51 ` [PATCH v2 2/2] target/i386: Use i128 for 128 and 256-bit loads and stores Richard Henderson
2023-10-17 11:52 ` [PATCH v2 0/2] tcg: Streamline vector load/store Philippe Mathieu-Daudé
2023-10-17 13:38 ` Richard Henderson [this message]
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