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([2602:47:d49d:ec01:986f:cb56:6709:4057]) by smtp.gmail.com with ESMTPSA id y18-20020a17090322d200b0016bedcced2fsm4037963plg.35.2022.09.28.09.45.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Sep 2022 09:45:22 -0700 (PDT) Message-ID: <697fb242-ba57-e00e-d824-b32f2bfc6c8a@linaro.org> Date: Wed, 28 Sep 2022 09:45:21 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v3 02/15] target/arm: ensure TCG IO accesses set appropriate MemTxAttrs Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell References: <20220927141504.3886314-1-alex.bennee@linaro.org> <20220927141504.3886314-3-alex.bennee@linaro.org> From: Richard Henderson In-Reply-To: <20220927141504.3886314-3-alex.bennee@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.319, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/27/22 07:14, Alex Bennée wrote: > Both arm_cpu_tlb_fill (for normal IO) and > arm_cpu_get_phys_page_attrs_debug (for debug access) come through > get_phys_addr which is setting the other memory attributes for the > transaction. As these are all by definition CPU accesses we can also > set the requested_type/index as appropriate. > > Signed-off-by: Alex Bennée > > --- > v3 > - reword commit summary > --- > target/arm/ptw.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target/arm/ptw.c b/target/arm/ptw.c > index 2ddfc028ab..4b0dc9bd14 100644 > --- a/target/arm/ptw.c > +++ b/target/arm/ptw.c > @@ -2289,6 +2289,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, > ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); > bool is_secure = regime_is_secure(env, mmu_idx); > > + attrs->requester_type = MEMTXATTRS_CPU; This shouldn't build since you renamed the enumerator. You should use *attrs = MEMTXATTRS_CPU(env_cpu(env)). r~