From: Richard Henderson <richard.henderson@linaro.org>
To: Ajeet Singh <itachis6234@gmail.com>, qemu-devel@nongnu.org
Cc: Mark Corbin <mark@dibsco.co.uk>, Warner Losh <imp@bsdimp.com>,
Ajeet Singh <itachis@FreeBSD.org>,
Jessica Clarke <jrtc27@jrtc27.com>,
Kyle Evans <kevans@FreeBSD.org>
Subject: Re: [PATCH v2 09/17] bsd-user: Add RISC-V thread setup and initialization support
Date: Mon, 19 Aug 2024 13:08:45 +1000 [thread overview]
Message-ID: <69dc62df-92d6-4dc1-8907-4f4533a08b36@linaro.org> (raw)
In-Reply-To: <20240816170949.238511-10-itachis@FreeBSD.org>
On 8/17/24 03:09, Ajeet Singh wrote:
> From: Mark Corbin <mark@dibsco.co.uk>
>
> Implemented functions for setting up and initializing threads in the
> RISC-V architecture.
> The 'target_thread_set_upcall' function sets up the stack pointer,
> program counter, and function argument for new threads.
> The 'target_thread_init' function initializes thread registers based on
> the provided image information.
>
> Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
> Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
> ---
> bsd-user/riscv/target_arch_thread.h | 47 +++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
> create mode 100644 bsd-user/riscv/target_arch_thread.h
>
> diff --git a/bsd-user/riscv/target_arch_thread.h b/bsd-user/riscv/target_arch_thread.h
> new file mode 100644
> index 0000000000..4596d3d51f
> --- /dev/null
> +++ b/bsd-user/riscv/target_arch_thread.h
> @@ -0,0 +1,47 @@
> +/*
> + * RISC-V thread support
> + *
> + * Copyright (c) 2019 Mark Corbin
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef TARGET_ARCH_THREAD_H
> +#define TARGET_ARCH_THREAD_H
> +
> +/* Compare with cpu_set_upcall() in riscv/riscv/vm_machdep.c */
> +static inline void target_thread_set_upcall(CPURISCVState *regs,
> + abi_ulong entry, abi_ulong arg, abi_ulong stack_base,
> + abi_ulong stack_size)
> +{
> + abi_ulong sp;
> +
> + sp = (abi_ulong)(stack_base + stack_size) & ~(16 - 1);
ROUND_DOWN(stack_base + stack_size, 16)
r~
next prev parent reply other threads:[~2024-08-19 3:09 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-16 17:09 [PATCH v2 00/17] bsd-user: Comprehensive RISCV Support Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 01/17] bsd-user: Implement RISC-V CPU initialization and main loop Ajeet Singh
2024-08-19 2:57 ` Richard Henderson
2024-08-16 17:09 ` [PATCH v2 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 04/17] bsd-user: Implement RISC-V TLS register setup Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 06/17] bsd-user: Define RISC-V register structures and register copying Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 07/17] bsd-user: Add RISC-V signal trampoline setup function Ajeet Singh
2024-08-19 3:06 ` Richard Henderson
2024-08-16 17:09 ` [PATCH v2 08/17] bsd-user: Implement RISC-V sysarch system call emulation Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 09/17] bsd-user: Add RISC-V thread setup and initialization support Ajeet Singh
2024-08-19 3:08 ` Richard Henderson [this message]
2024-08-16 17:09 ` [PATCH v2 10/17] bsd-user: Define RISC-V VM parameters and helper functions Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 11/17] bsd-user: Define RISC-V system call structures and constants Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 12/17] bsd-user: Add generic RISC-V64 target definitions Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 13/17] bsd-user: Define RISC-V signal handling structures and constants Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 14/17] bsd-user: Implement RISC-V signal trampoline setup functions Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 15/17] bsd-user: Implement 'get_mcontext' for RISC-V Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Ajeet Singh
2024-08-16 17:09 ` [PATCH v2 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Ajeet Singh
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