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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id u123sm4586602pfb.109.2019.12.11.18.26.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Dec 2019 18:26:26 -0800 (PST) Subject: Re: [PATCH v3 12/20] target/arm: generate xml description of our SVE registers To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org References: <20191211170520.7747-1-alex.bennee@linaro.org> <20191211170520.7747-13-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <69e10c48-8bdf-cbe0-3372-815b647f8312@linaro.org> Date: Wed, 11 Dec 2019 18:26:24 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191211170520.7747-13-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: damien.hedde@greensocs.com, Peter Maydell , "open list:ARM TCG CPUs" , luis.machado@linaro.org, alan.hayward@arm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/11/19 9:05 AM, Alex Bennée wrote: > +static struct TypeSize vec_lanes[] = { const. > + case 51: > + return gdb_get_reg64(buf, (cpu->env.vfp.zcr_el[1] & 0xf) + 1); You need to use sve_zcr_len_for_el to get the effective vq. Also, I thought vg == 2 * vq. > + case 51: > + { > + uint64_t val = *(uint64_t *) buf; > + cpu->env.vfp.zcr_el[1] = (val - 1) & 0xf; You cannot hard-code EL1 without ifdef CONFIG_USER_ONLY. If the effective vq decreases, you must call aarch64_sve_narrow_vq. You must call arm_rebuild_hflags. r~