From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=38578 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1POI3K-00042V-Ll for qemu-devel@nongnu.org; Thu, 02 Dec 2010 17:55:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1POI3J-0001f3-Bl for qemu-devel@nongnu.org; Thu, 02 Dec 2010 17:55:02 -0500 Received: from mx1.redhat.com ([209.132.183.28]:55685) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1POI3I-0001ey-Vl for qemu-devel@nongnu.org; Thu, 02 Dec 2010 17:55:01 -0500 Date: Fri, 3 Dec 2010 00:54:43 +0200 From: "Michael S. Tsirkin" Message-ID: <6a342f04f29de984ba43f49722d9d8d2fdc3147b.1291330353.git.mst@redhat.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: [Qemu-devel] [PATCH 5/6] pci/aer: fix interrupt on config write List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: yamahata@valinux.co.jp, qemu-devel@nongnu.org config write handling for aer seems broken: For example, it won't clear a level interrupt when command register is set to 0. Make it match the spec: level should equal the logical or of enabled bits, msi only be sent when the logical or changes. Signed-off-by: Michael S. Tsirkin --- hw/pcie_aer.c | 46 +++++++++++++++++----------------------------- 1 files changed, 17 insertions(+), 29 deletions(-) diff --git a/hw/pcie_aer.c b/hw/pcie_aer.c index 0fc191f..1c513a7 100644 --- a/hw/pcie_aer.c +++ b/hw/pcie_aer.c @@ -749,43 +749,31 @@ void pcie_aer_root_reset(PCIDevice *dev) */ } -static bool pcie_aer_root_does_trigger(uint32_t cmd, uint32_t status) -{ - return - ((cmd & PCI_ERR_ROOT_CMD_COR_EN) && (status & PCI_ERR_ROOT_COR_RCV)) || - ((cmd & PCI_ERR_ROOT_CMD_NONFATAL_EN) && - (status & PCI_ERR_ROOT_NONFATAL_RCV)) || - ((cmd & PCI_ERR_ROOT_CMD_FATAL_EN) && - (status & PCI_ERR_ROOT_FATAL_RCV)); -} - void pcie_aer_root_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len, uint32_t root_cmd_prev) { uint8_t *aer_cap = dev->config + dev->exp.aer_cap; - - /* root command register */ + uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); + uint32_t enabled_cmd = pcie_aer_status_to_cmd(root_status); uint32_t root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND); - if (root_cmd & PCI_ERR_ROOT_CMD_EN_MASK) { - /* 6.2.4.1.2 Interrupt Generation */ + /* 6.2.4.1.2 Interrupt Generation */ + if (!msix_enabled(dev) && !msi_enabled(dev)) { + qemu_set_irq(dev->irq[dev->exp.aer_intx], !!(root_cmd & enabled_cmd)); + return; + } - /* 0 -> 1 */ - uint32_t root_cmd_set = ~root_cmd_prev & root_cmd; - uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); - bool assert = pcie_aer_root_does_trigger(root_cmd_set, root_status); + if ((root_cmd_prev & enabled_cmd) || !(root_cmd & enabled_cmd)) { + /* Send MSI on transition from false to true. */ + return; + } - if (msix_enabled(dev)) { - if (assert) { - msix_notify(dev, pcie_aer_root_get_vector(dev)); - } - } else if (msi_enabled(dev)) { - if (assert) { - msi_notify(dev, pcie_aer_root_get_vector(dev)); - } - } else { - qemu_set_irq(dev->irq[dev->exp.aer_intx], assert); - } + if (msix_enabled(dev)) { + msix_notify(dev, pcie_aer_root_get_vector(dev)); + } else if (msi_enabled(dev)) { + msi_notify(dev, pcie_aer_root_get_vector(dev)); + } else { + assert(0); } } -- 1.7.3.2.91.g446ac