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Tue, 19 Oct 2021 12:10:16 -0700 (PDT) Subject: Re: [PATCH 02/31] target/loongarch: Add CSR registers definition To: Xiaojuan Yang , qemu-devel@nongnu.org References: <1634628917-10031-1-git-send-email-yangxiaojuan@loongson.cn> <1634628917-10031-3-git-send-email-yangxiaojuan@loongson.cn> From: Richard Henderson Message-ID: <6a5d3208-e9a8-0dd0-f41d-18678ae50b9b@linaro.org> Date: Tue, 19 Oct 2021 12:10:14 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <1634628917-10031-3-git-send-email-yangxiaojuan@loongson.cn> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.074, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, thuth@redhat.com, chenhuacai@loongson.cn, mst@redhat.com, philmd@redhat.com, mark.cave-ayland@ilande.co.uk, laurent@vivier.eu, peterx@redhat.com, f4bug@amsat.org, alistair.francis@wdc.com, maobibo@loongson.cn, gaosong@loongson.cn, pbonzini@redhat.com, bmeng.cn@gmail.com, alex.bennee@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/19/21 12:34 AM, Xiaojuan Yang wrote: > +/* > + * All Possible CSR registers used by tcg > + * > + * default value in target/loongarch/cpu.c > + * > + * This macro will be used only in: > + * > target/loongarch/cpu.h:CPULoongArchState > + * > + * during translate: > + * > helper_csr_rdq() > + * > helper_csr_wrq() > + * > helper_csr_xchgq() > + * > helper_csr_xchgq_r0() > + */ > +#define CPU_LOONGARCH_CSR \ > + uint64_t CSR_CRMD; \ > + uint64_t CSR_PRMD; \ I don't see the point in this macro. Just put the structure members directly into CPULoongArchState. In addition, I think you'll want to include these members unconditionally. We have found for ARM that it is easiest to minimize the differences between system and user emulation. Having to ifdef each use of the csrs does not help. r~