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Mon, 25 Jan 2021 14:55:33 +0000 (GMT) Received: from oc4221205838.ibm.com (unknown [9.211.138.51]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Mon, 25 Jan 2021 14:55:33 +0000 (GMT) Subject: Re: [PATCH 0/8] s390x/pci: Fixing s390 vfio-pci ISM support To: Cornelia Huck References: <1611089059-6468-1-git-send-email-mjrosato@linux.ibm.com> <511aebd3-fc4f-d7d3-32c2-27720fb38fe8@linux.ibm.com> <15dbd981-7dda-2526-8f13-52ead6298ef1@linux.ibm.com> <914d4af3-32ee-e300-9738-92aececa81d6@linux.ibm.com> <789388f4-983b-2810-7f46-ce7f07022a66@linux.ibm.com> <213c00ca-1b8f-ecee-dd22-d86cad8eb63b@linux.ibm.com> <4a3e13fe-ec6a-27bc-7f30-9ad9691a4522@linux.ibm.com> <9522792d-6677-eed4-f480-4efaaf00dd51@linux.ibm.com> <20210121185036.41fde30c.cohuck@redhat.com> <60a2efe8-ff3d-6ea5-230c-408995eaf016@linux.ibm.com> <20210122174606.07bb1c68.cohuck@redhat.com> From: Matthew Rosato Message-ID: <6a7074f8-e040-14c1-c43b-83e9e39c3975@linux.ibm.com> Date: Mon, 25 Jan 2021 09:55:33 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210122174606.07bb1c68.cohuck@redhat.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-25_04:2021-01-25, 2021-01-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 spamscore=0 mlxscore=0 malwarescore=0 phishscore=0 adultscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2101250081 Received-SPF: pass client-ip=148.163.158.5; envelope-from=mjrosato@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, Pierre Morel , david@redhat.com, Niklas Schnelle , richard.henderson@linaro.org, qemu-s390x@nongnu.org, qemu-devel@nongnu.org, pasic@linux.ibm.com, borntraeger@de.ibm.com, alex.williamson@redhat.com, mst@redhat.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/22/21 11:46 AM, Cornelia Huck wrote: > On Thu, 21 Jan 2021 13:06:24 -0500 > Matthew Rosato wrote: > >> On 1/21/21 12:50 PM, Cornelia Huck wrote: >>> On Thu, 21 Jan 2021 15:54:22 +0100 >>> Niklas Schnelle wrote: >>> >>>> On 1/21/21 3:46 PM, Pierre Morel wrote: >>>>> >>>>> >>>>> On 1/21/21 2:37 PM, Niklas Schnelle wrote: >>>>>> >>>>>> >>>>>> On 1/21/21 1:30 PM, Pierre Morel wrote: >>>>> >>>>>>>> >>>>>>>> Just wanted to say that we've had a very similar discussion with >>>>>>>> Cornelia end of last year and came to the conclusion that explicitly >>>>>>>> matching the PFT is likely the safest bet: >>>>>>>> https://lkml.org/lkml/2020/12/22/479 >>>>>>> >>>>>>> What I see there is a discussion on the relation between relaxed access and MIO without explaining to Connie that we have in the kernel the possibility to know if a device support MIO or not independently of it supports the relaxed access. >>>>>>> >>>>>>> The all point here is about taking decisions for the right reasons. >>>>>>> >>>>>>> We have the possibility to take the decision based on functionalities and not on a specific PCI function. >>>>>> >>>>>> Yes but that goes both ways the functionality of the region has to match >>>>>> that of the device and at least in it's current state the regions functionality >>>>>> matches only ISM in a way that is so specific that it is very unlikely to match anything >>>>>> else. For example it can't support a PCI device that requires non-MIO but >>>>>> also MSI-X. In its current form it doesn't even support PCI Store only PCI Store >>>>>> Block, we had that in an earlier version and it's trivial but then we get the MSI-X >>>>>> problem. >>>>> >>>>> >>>>> What does that change if we take one or the other solution considering the checking of MIO/MSIX/relax versus PFT? >>>> >>>> >>>> If it's !MIO && !MSIX && relax_align I'm fine with that check but >>>> then we should also add PCISTG to the region. >>>> >>> >>> Just to double check: that would today cover only ISM (which doesn't >>> use PCISTG), correct? >>> >> >> Yes, correct -- So to summarize the proposal outlined is to use those >> features to determine whether a device should be using the region or not >> rather rather than strictly saying only PFT==ISM may use it. >> >> Practically speaking, ISM is the only device that fits the bill today >> when you combine these things, and ISM does not use PCISTG -- so PCISTG >> support was simply omitted from the region (prior versions before coming >> upstream included it, was dropped since ISM doesn't use it). >> >> What Niklas suggests here is that, if we are going to be broad in >> determining whether the region can be used for a given device vs saying >> 'only PFT==ISM', then we can no longer assume that the device doesn't >> use PCISTG and as such is suggesting the region should also include >> PCISTG support as a means of future compatibility (to ensure non-MIO >> PCISTG is issued for the device). > > Yes, if we go the "check for features" route, including PCISTG makes > sense. > > However, I'm still not quite sure whether checking for ISM vs checking > for features makes more sense in the long run. Is ISM that one weird > device whose cousins you're not going to invite to the party, or is ... Yes. :) > there a possibility that there will be devices that could make use of > the region for performance etc.? > Also yes. Well, potentially. That's really what I wanted at the outset, but the fly in the ointment is that the region as I exploit it in QEMU today only works properly for devices without MSI-X, which frankly limits its general-purpose utility. If we could lift that restriction (whether it be now or at a later point) then the region becomes quite beneficial for performance of any devices making frequent use of large PCISTB operations.