Re: [PATCH] RISC-V: fcvt can set fflags, so set FS accordingly

[Richard Henderson <richard.henderson@linaro.org>]

On 10/9/19 5:15 PM, Palmer Dabbelt wrote:
> A user pinged me to say "my floating point heavy code works in user mode
> but not system mode", which I'm guessing is the result of a lazy FP
> save/restore issue as those still crop up from time to time as long tail
> bugs.  I figured it was worth giving the FP stuff a look to see if
> anything jumps out, and it turns out that there is a bug: converting
> float to integer can set the invalid flag, which is supposed to mark FS
> as dirty, but the emulation routine doesn't do so.
> 
> This patch unconditionally marks FS as dirty for fcvt instructions that
> convert into X registers (fcvt into F registers already did so).  I
> haven't actually tried to manifest a bug here, but as far as I can tell
> the soft float stuff does set the invalid flag.
> 
> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
> ---
>  target/riscv/insn_trans/trans_rvd.inc.c | 2 ++
>  target/riscv/insn_trans/trans_rvf.inc.c | 4 ++++
>  2 files changed, 6 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~