* [Qemu-devel] [PATCH v7 00/12] data-driven device registers
@ 2016-06-22 20:23 Alistair Francis
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 01/12] bitops: Add MAKE_64BIT_MASK macro Alistair Francis
` (10 more replies)
0 siblings, 11 replies; 27+ messages in thread
From: Alistair Francis @ 2016-06-22 20:23 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: alistair.francis, crosthwaitepeter, edgar.iglesias,
edgar.iglesias, afaerber, fred.konrad, alex.bennee
This patch series is based on Peter C's original register API. His
original cover letter is below.
Future work: Allow support for memory attributes.
V7:
- Rebase
- Fixup the DecCFG model
- Fixes and corrections to the register API model and functions
V6:
- Small changes to the API based on Alex's comments
- Remove 'register: Add support for decoding information' patch
- Move prefix and debug into the RegisterInfoArray as it is the same
for every register.
V5:
- Only create a single memory region instead of a memory region for
each register
- General tidyups based on Alex's comments
V4:
- Rebase and fix build issue
- Simplify the register write logic
- Other small fixes suggested by Alex Bennee
V3:
- Small changes reported by Fred
V2:
- Rebase
- Fix up IOU SLCR connections
- Add the memory_region_add_subregion_no_print() function and use it
for the registers
Changes since RFC:
- Connect the ZynqMP IOU SLCR device
- Rebase
Original cover letter From Peter:
Hi All. This is a new scheme I've come up with handling device registers in a
data driven way. My motivation for this is to factor out a lot of the access
checking that seems to be replicated in every device. See P1 commit message for
further discussion.
P1 is the main patch, adds the register definition functionality
P2-3,6 add helpers that glue the register API to the Memory API
P4 Defines a set of macros that minimise register and field definitions
P5 is QOMfication
P7 is a trivial
P10-13 Work up to GPIO support
P8,9,14 add new devices (the Xilinx Zynq devcfg & ZynqMP SLCR) that use this
scheme.
P15: Connect the ZynqMP SLCR device
This Zynq devcfg device was particularly finnicky with per-bit restrictions.
I'm also looking for a higher-than-usual modelling fidelity
on the register space, with semantics defined for random reserved bits
in-between otherwise consistent fields.
Here's an example of the qemu_log output for the devcfg device. This is produced
by now generic sharable code:
/machine/unattached/device[44]:Addr 0x000008:CFG: write of value 00000508
/machine/unattached/device[44]:Addr 0x000080:MCTRL: write of value 00800010
/machine/unattached/device[44]:Addr 0x000010:INT_MASK: write of value ffffffff
/machine/unattached/device[44]:Addr 00000000:CTRL: write of value 0c00607f
And an example of a rogue guest banging on a bad bit:
/machine/unattached/device[44]:Addr 0x000014:STATUS bits 0x000001 may not be \
written to 1
A future feature I am interested in is implementing TCG optimisation of
side-effectless registers. The register API allows clear definition of
what registers have txn side effects and which ones don't. You could even
go a step further and translate such side-effectless accesses based on the
data pointer for the register.
Alistair Francis (6):
bitops: Add MAKE_64BIT_MASK macro
register: Add Register API
register: Add Memory API glue
dma: Add Xilinx Zynq devcfg device model
register: Add GPIO API
xlnx-zynqmp: Connect the ZynqMP IOU SLCR
Peter Crosthwaite (6):
register: Define REG and FIELD macros
register: QOMify
register: Add block initialise helper
xilinx_zynq: Connect devcfg to the Zynq machine model
irq: Add opaque setter routine
misc: Introduce ZynqMP IOU SLCR
default-configs/arm-softmmu.mak | 1 +
hw/arm/xilinx_zynq.c | 6 +
hw/arm/xlnx-zynqmp.c | 14 ++
hw/core/Makefile.objs | 1 +
hw/core/irq.c | 5 +
hw/core/register.c | 370 ++++++++++++++++++++++++++++++
hw/dma/Makefile.objs | 1 +
hw/dma/xlnx-zynq-devcfg.c | 401 +++++++++++++++++++++++++++++++++
hw/misc/Makefile.objs | 1 +
hw/misc/xlnx-zynqmp-iou-slcr.c | 122 ++++++++++
include/hw/arm/xlnx-zynqmp.h | 2 +
include/hw/dma/xlnx-zynq-devcfg.h | 62 +++++
include/hw/irq.h | 2 +
include/hw/misc/xlnx-zynqmp-iou-slcr.h | 47 ++++
include/hw/register.h | 263 +++++++++++++++++++++
include/qemu/bitops.h | 3 +
16 files changed, 1301 insertions(+)
create mode 100644 hw/core/register.c
create mode 100644 hw/dma/xlnx-zynq-devcfg.c
create mode 100644 hw/misc/xlnx-zynqmp-iou-slcr.c
create mode 100644 include/hw/dma/xlnx-zynq-devcfg.h
create mode 100644 include/hw/misc/xlnx-zynqmp-iou-slcr.h
create mode 100644 include/hw/register.h
--
2.7.4
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH v7 01/12] bitops: Add MAKE_64BIT_MASK macro
2016-06-22 20:23 [Qemu-devel] [PATCH v7 00/12] data-driven device registers Alistair Francis
@ 2016-06-22 20:23 ` Alistair Francis
2016-06-23 12:14 ` Peter Maydell
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 02/12] register: Add Register API Alistair Francis
` (9 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Alistair Francis @ 2016-06-22 20:23 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: alistair.francis, crosthwaitepeter, edgar.iglesias,
edgar.iglesias, afaerber, fred.konrad, alex.bennee
Add a macro that creates a 64bit value which has length number of ones
shifted across by the value of shift.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
V7:
- Fixup commit typo
- Use the method from deposit64()
V5:
- Re-write to a 64-bit mask instead of ONES()
- Re-order this patch in the series
include/qemu/bitops.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 15418a8..98fb005 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -24,6 +24,9 @@
#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+#define MAKE_64BIT_MASK(shift, length) \
+ (((~0ULL) >> (64 - (length))) << (shift))
+
/**
* set_bit - Set a bit in memory
* @nr: the bit to set
--
2.7.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH v7 02/12] register: Add Register API
2016-06-22 20:23 [Qemu-devel] [PATCH v7 00/12] data-driven device registers Alistair Francis
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 01/12] bitops: Add MAKE_64BIT_MASK macro Alistair Francis
@ 2016-06-22 20:23 ` Alistair Francis
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 03/12] register: Add Memory API glue Alistair Francis
` (8 subsequent siblings)
10 siblings, 0 replies; 27+ messages in thread
From: Alistair Francis @ 2016-06-22 20:23 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: alistair.francis, crosthwaitepeter, edgar.iglesias,
edgar.iglesias, afaerber, fred.konrad, alex.bennee
This API provides some encapsulation of registers and factors out some
common functionality to common code. Bits of device state (usually MMIO
registers) often have all sorts of access restrictions and semantics
associated with them. This API allows you to define what those
restrictions are on a bit-by-bit basis.
Helper functions are then used to access the register which observe the
semantics defined by the RegisterAccessInfo struct.
Some features:
Bits can be marked as read_only (ro field)
Bits can be marked as write-1-clear (w1c field)
Bits can be marked as reserved (rsvd field)
Reset values can be defined (reset)
Bits can be marked clear on read (cor)
Pre and post action callbacks can be added to read and write ops
Verbose debugging info can be enabled/disabled
Useful for defining device register spaces in a data driven way. Cuts
down on a lot of the verbosity and repetition in the switch-case blocks
in the standard foo_mmio_read/write functions.
Also useful for automated generation of device models from hardware
design sources.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
V5:
- Convert to using only one memory region
V4:
- Rebase
- Remove the guest error masking
- Simplify the unimplemented masking
- Use the reserved value in the write calculations
- Remove read_lite and write_lite
- General fixes to asserts and log printing
V3:
- Address some comments from Fred
hw/core/Makefile.objs | 1 +
hw/core/register.c | 156 ++++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/register.h | 110 +++++++++++++++++++++++++++++++++++
3 files changed, 267 insertions(+)
create mode 100644 hw/core/register.c
create mode 100644 include/hw/register.h
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
index 82a9ef8..cfd4840 100644
--- a/hw/core/Makefile.objs
+++ b/hw/core/Makefile.objs
@@ -15,4 +15,5 @@ common-obj-$(CONFIG_SOFTMMU) += machine.o
common-obj-$(CONFIG_SOFTMMU) += null-machine.o
common-obj-$(CONFIG_SOFTMMU) += loader.o
common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o
+common-obj-$(CONFIG_SOFTMMU) += register.o
common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o
diff --git a/hw/core/register.c b/hw/core/register.c
new file mode 100644
index 0000000..cc067f1
--- /dev/null
+++ b/hw/core/register.c
@@ -0,0 +1,156 @@
+/*
+ * Register Definition API
+ *
+ * Copyright (c) 2016 Xilinx Inc.
+ * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/register.h"
+#include "hw/qdev.h"
+#include "qemu/log.h"
+
+static inline void register_write_val(RegisterInfo *reg, uint64_t val)
+{
+ g_assert(reg->data);
+
+ switch (reg->data_size) {
+ case 1:
+ *(uint8_t *)reg->data = val;
+ break;
+ case 2:
+ *(uint16_t *)reg->data = val;
+ break;
+ case 4:
+ *(uint32_t *)reg->data = val;
+ break;
+ case 8:
+ *(uint64_t *)reg->data = val;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static inline uint64_t register_read_val(RegisterInfo *reg)
+{
+ switch (reg->data_size) {
+ case 1:
+ return *(uint8_t *)reg->data;
+ case 2:
+ return *(uint16_t *)reg->data;
+ case 4:
+ return *(uint32_t *)reg->data;
+ case 8:
+ return *(uint64_t *)reg->data;
+ default:
+ g_assert_not_reached();
+ }
+ return 0; /* unreachable */
+}
+
+void register_write(RegisterInfo *reg, uint64_t val, uint64_t we,
+ const char *prefix, bool debug)
+{
+ uint64_t old_val, new_val, test, no_w_mask;
+ const RegisterAccessInfo *ac;
+
+ assert(reg);
+
+ ac = reg->access;
+
+ if (!ac || !ac->name) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: write to undefined device state "
+ "(written value: %#" PRIx64 ")\n", prefix, val);
+ return;
+ }
+
+ old_val = reg->data ? register_read_val(reg) : ac->reset;
+
+ test = (old_val ^ val) & ac->rsvd;
+ if (test) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: change of value in reserved bit"
+ "fields: %#" PRIx64 ")\n", prefix, test);
+ }
+
+ test = val & ac->unimp;
+ if (test) {
+ qemu_log_mask(LOG_UNIMP,
+ "%s:%s writing %#" PRIx64 " to unimplemented bits:" \
+ " %#" PRIx64 "",
+ prefix, reg->access->name, val, ac->unimp);
+ }
+
+ /* Create the no write mask based on the read only, write to clear and
+ * reserved bit masks.
+ */
+ no_w_mask = ac->ro | ac->w1c | ac->rsvd | ~we;
+ new_val = (val & ~no_w_mask) | (old_val & no_w_mask);
+ new_val &= ~(val & ac->w1c);
+
+ if (ac->pre_write) {
+ new_val = ac->pre_write(reg, new_val);
+ }
+
+ if (debug) {
+ qemu_log("%s:%s: write of value %#" PRIx64 "\n", prefix, ac->name,
+ new_val);
+ }
+
+ register_write_val(reg, new_val);
+
+ if (ac->post_write) {
+ ac->post_write(reg, new_val);
+ }
+}
+
+uint64_t register_read(RegisterInfo *reg, const char* prefix, bool debug)
+{
+ uint64_t ret;
+ const RegisterAccessInfo *ac;
+
+ assert(reg);
+
+ ac = reg->access;
+ if (!ac || !ac->name) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: read from undefined device state\n",
+ prefix);
+ return 0;
+ }
+
+ ret = reg->data ? register_read_val(reg) : ac->reset;
+
+ register_write_val(reg, ret & ~ac->cor);
+
+ if (ac->post_read) {
+ ret = ac->post_read(reg, ret);
+ }
+
+ if (debug) {
+ qemu_log("%s:%s: read of value %#" PRIx64 "\n", prefix,
+ ac->name, ret);
+ }
+
+ return ret;
+}
+
+void register_reset(RegisterInfo *reg)
+{
+ g_assert(reg);
+
+ if (!reg->data || !reg->access) {
+ return;
+ }
+
+ register_write_val(reg, reg->access->reset);
+}
diff --git a/include/hw/register.h b/include/hw/register.h
new file mode 100644
index 0000000..04c6f47
--- /dev/null
+++ b/include/hw/register.h
@@ -0,0 +1,110 @@
+/*
+ * Register Definition API
+ *
+ * Copyright (c) 2016 Xilinx Inc.
+ * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#ifndef REGISTER_H
+#define REGISTER_H
+
+#include "exec/memory.h"
+
+typedef struct RegisterInfo RegisterInfo;
+typedef struct RegisterAccessInfo RegisterAccessInfo;
+
+/**
+ * Access description for a register that is part of guest accessible device
+ * state.
+ *
+ * @name: String name of the register
+ * @ro: whether or not the bit is read-only
+ * @w1c: bits with the common write 1 to clear semantic.
+ * @reset: reset value.
+ * @cor: Bits that are clear on read
+ * @rsvd: Bits that are reserved and should not be changed
+ *
+ * @pre_write: Pre write callback. Passed the value that's to be written,
+ * immediately before the actual write. The returned value is what is written,
+ * giving the handler a chance to modify the written value.
+ * @post_write: Post write callback. Passed the written value. Most write side
+ * effects should be implemented here.
+ *
+ * @post_read: Post read callback. Passes the value that is about to be returned
+ * for a read. The return value from this function is what is ultimately read,
+ * allowing this function to modify the value before return to the client.
+ */
+
+struct RegisterAccessInfo {
+ const char *name;
+ uint64_t ro;
+ uint64_t w1c;
+ uint64_t reset;
+ uint64_t cor;
+ uint64_t rsvd;
+ uint64_t unimp;
+
+ uint64_t (*pre_write)(RegisterInfo *reg, uint64_t val);
+ void (*post_write)(RegisterInfo *reg, uint64_t val);
+
+ uint64_t (*post_read)(RegisterInfo *reg, uint64_t val);
+};
+
+/**
+ * A register that is part of guest accessible state
+ * @data: pointer to the register data. Will be cast
+ * to the relevant uint type depending on data_size.
+ * @data_size: Size of the register in bytes. Must be
+ * 1, 2, 4 or 8
+ *
+ * @access: Access description of this register
+ *
+ * @debug: Whether or not verbose debug is enabled
+ * @prefix: String prefix for log and debug messages
+ *
+ * @opaque: Opaque data for the register
+ */
+
+struct RegisterInfo {
+ /* <public> */
+ void *data;
+ int data_size;
+
+ const RegisterAccessInfo *access;
+
+ void *opaque;
+};
+
+/**
+ * write a value to a register, subject to its restrictions
+ * @reg: register to write to
+ * @val: value to write
+ * @we: write enable mask
+ * @prefix: The device prefix that should be printed before the register name
+ * @debug: Should the write operation debug information be printed?
+ */
+
+void register_write(RegisterInfo *reg, uint64_t val, uint64_t we,
+ const char *prefix, bool debug);
+
+/**
+ * read a value from a register, subject to its restrictions
+ * @reg: register to read from
+ * @prefix: The device prefix that should be printed before the register name
+ * @debug: Should the read operation debug information be printed?
+ * returns: value read
+ */
+
+uint64_t register_read(RegisterInfo *reg, const char* prefix, bool debug);
+
+/**
+ * reset a register
+ * @reg: register to reset
+ */
+
+void register_reset(RegisterInfo *reg);
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH v7 03/12] register: Add Memory API glue
2016-06-22 20:23 [Qemu-devel] [PATCH v7 00/12] data-driven device registers Alistair Francis
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 01/12] bitops: Add MAKE_64BIT_MASK macro Alistair Francis
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 02/12] register: Add Register API Alistair Francis
@ 2016-06-22 20:23 ` Alistair Francis
2016-06-23 12:21 ` Peter Maydell
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 04/12] register: Define REG and FIELD macros Alistair Francis
` (7 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Alistair Francis @ 2016-06-22 20:23 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: alistair.francis, crosthwaitepeter, edgar.iglesias,
edgar.iglesias, afaerber, fred.konrad, alex.bennee
Add memory io handlers that glue the register API to the memory API.
Just translation functions at this stage. Although it does allow for
devices to be created without all-in-one mmio r/w handlers.
This patch also adds the RegisterInfoArray struct, which allows all of
the individual RegisterInfo structs to be grouped into a single memory
region.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V7:
- Remove endianess handling
- Remove assert() and log missing registers
V6:
- Add the memory region later
V5:
- Convert to using only one memory region
hw/core/register.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/register.h | 43 ++++++++++++++++++++++++++++++++++++++
2 files changed, 101 insertions(+)
diff --git a/hw/core/register.c b/hw/core/register.c
index cc067f1..149aebb 100644
--- a/hw/core/register.c
+++ b/hw/core/register.c
@@ -154,3 +154,61 @@ void register_reset(RegisterInfo *reg)
register_write_val(reg, reg->access->reset);
}
+
+void register_write_memory(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
+{
+ RegisterInfoArray *reg_array = opaque;
+ RegisterInfo *reg = NULL;
+ uint64_t we = ~0;
+ int i;
+
+ for (i = 0; i < reg_array->num_elements; i++) {
+ if (reg_array->r[i]->access->addr == addr) {
+ reg = reg_array->r[i];
+ break;
+ }
+ }
+
+ if (!reg) {
+ qemu_log_mask(LOG_UNIMP, "Write to unimplemented register at " \
+ "address: %#" PRIx64 "\n", addr);
+ return;
+ }
+
+ /* Generate appropriate write enable mask */
+ if (reg->data_size < size) {
+ we = MAKE_64BIT_MASK(0, reg->data_size * 8);
+ } else if (reg->data_size >= size) {
+ we = MAKE_64BIT_MASK(0, size * 8);
+ }
+
+ register_write(reg, value, we, reg_array->prefix,
+ reg_array->debug);
+}
+
+uint64_t register_read_memory(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ RegisterInfoArray *reg_array = opaque;
+ RegisterInfo *reg = NULL;
+ uint64_t read_val;
+ int i;
+
+ for (i = 0; i < reg_array->num_elements; i++) {
+ if (reg_array->r[i]->access->addr == addr) {
+ reg = reg_array->r[i];
+ break;
+ }
+ }
+
+ if (!reg) {
+ qemu_log_mask(LOG_UNIMP, "Read to unimplemented register at " \
+ "address: %#" PRIx64 "\n", addr);
+ return 0;
+ }
+
+ read_val = register_read(reg, reg_array->prefix, reg_array->debug);
+
+ return extract64(read_val, 0, size * 8);
+}
diff --git a/include/hw/register.h b/include/hw/register.h
index 04c6f47..e160150 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -15,6 +15,7 @@
typedef struct RegisterInfo RegisterInfo;
typedef struct RegisterAccessInfo RegisterAccessInfo;
+typedef struct RegisterInfoArray RegisterInfoArray;
/**
* Access description for a register that is part of guest accessible device
@@ -51,6 +52,8 @@ struct RegisterAccessInfo {
void (*post_write)(RegisterInfo *reg, uint64_t val);
uint64_t (*post_read)(RegisterInfo *reg, uint64_t val);
+
+ hwaddr addr;
};
/**
@@ -79,6 +82,25 @@ struct RegisterInfo {
};
/**
+ * This structure is used to group all of the individual registers which are
+ * modeled using the RegisterInfo strucutre.
+ *
+ * @r is an aray containing of all the relevent RegisterInfo structures.
+ *
+ * @num_elements is the number of elements in the array r
+ *
+ * @mem: optional Memory region for the register
+ */
+
+struct RegisterInfoArray {
+ int num_elements;
+ RegisterInfo **r;
+
+ bool debug;
+ const char *prefix;
+};
+
+/**
* write a value to a register, subject to its restrictions
* @reg: register to write to
* @val: value to write
@@ -107,4 +129,25 @@ uint64_t register_read(RegisterInfo *reg, const char* prefix, bool debug);
void register_reset(RegisterInfo *reg);
+/**
+ * Memory API MMIO write handler that will write to a Register API register.
+ * @opaque: RegisterInfo to write to
+ * @addr: Address to write
+ * @value: Value to write
+ * @size: Number of bytes to write
+ */
+
+void register_write_memory(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size);
+
+/**
+ * Memory API MMIO read handler that will read from a Register API register.
+ * @opaque: RegisterInfo to read from
+ * @addr: Address to read
+ * @size: Number of bytes to read
+ * returns: Value read from register
+ */
+
+uint64_t register_read_memory(void *opaque, hwaddr addr, unsigned size);
+
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH v7 04/12] register: Define REG and FIELD macros
2016-06-22 20:23 [Qemu-devel] [PATCH v7 00/12] data-driven device registers Alistair Francis
` (2 preceding siblings ...)
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 03/12] register: Add Memory API glue Alistair Francis
@ 2016-06-22 20:23 ` Alistair Francis
2016-06-23 12:39 ` Peter Maydell
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 05/12] register: QOMify Alistair Francis
` (6 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Alistair Francis @ 2016-06-22 20:23 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: alistair.francis, crosthwaitepeter, edgar.iglesias,
edgar.iglesias, afaerber, fred.konrad, alex.bennee
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Define some macros that can be used for defining registers and fields.
The REG32 macro will define A_FOO, for the byte address of a register
as well as R_FOO for the uint32_t[] register number (A_FOO / 4).
The FIELD macro will define FOO_BAR_MASK, FOO_BAR_SHIFT and
FOO_BAR_LENGTH constants for field BAR in register FOO.
Finally, there are some shorthand helpers for extracting/depositing
fields from registers based on these naming schemes.
Usage can greatly reduce the verbosity of device code.
The deposit and extract macros (eg FIELD_EX32, FIELD_DP32 etc.) can be
used to generate extract and deposits without any repetition of the name
stems.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
[ EI Changes:
* Add Deposit macros
]
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
E.g. Currently you have to define something like:
\#define R_FOOREG (0x84/4)
\#define R_FOOREG_BARFIELD_SHIFT 10
\#define R_FOOREG_BARFIELD_LENGTH 5
uint32_t foobar_val = extract32(s->regs[R_FOOREG],
R_FOOREG_BARFIELD_SHIFT,
R_FOOREG_BARFIELD_LENGTH);
Which has:
2 macro definitions per field
3 register names ("FOOREG") per extract
2 field names ("BARFIELD") per extract
With these macros this becomes:
REG32(FOOREG, 0x84)
FIELD(FOOREG, BARFIELD, 10, 5)
uint32_t foobar_val = ARRAY_FIELD_EX32(s->regs, FOOREG, BARFIELD)
Which has:
1 macro definition per field
1 register name per extract
1 field name per extract
If you are not using arrays for the register data you can just use the
non-array "FIELD_" variants and still save 2 name stems:
uint32_t foobar_val = FIELD_EX32(s->fooreg, FOOREG, BARFIELD)
Deposit is similar for depositing values. Deposit has compile-time
overflow checking for literals.
For example:
REG32(XYZ1, 0x84)
FIELD(XYZ1, TRC, 0, 4)
/* Correctly set XYZ1.TRC = 5. */
ARRAY_FIELD_DP32(s->regs, XYZ1, TRC, 5);
/* Incorrectly set XYZ1.TRC = 16. */
ARRAY_FIELD_DP32(s->regs, XYZ1, TRC, 16);
The latter assignment results in:
warning: large integer implicitly truncated to unsigned type [-Woverflow]
include/hw/register.h | 43 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/include/hw/register.h b/include/hw/register.h
index e160150..216b679 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -150,4 +150,47 @@ void register_write_memory(void *opaque, hwaddr addr, uint64_t value,
uint64_t register_read_memory(void *opaque, hwaddr addr, unsigned size);
+/* Define constants for a 32 bit register */
+
+/* This macro will define A_FOO, for the byte address of a register
+ * as well as R_FOO for the uint32_t[] register number (A_FOO / 4).
+ */
+#define REG32(reg, addr) \
+ enum { A_ ## reg = (addr) }; \
+ enum { R_ ## reg = (addr) / 4 };
+
+/* Define SHIFT, LEGTH and MASK constants for a field within a register */
+
+/* This macro will define FOO_BAR_MASK, FOO_BAR_SHIFT and FOO_BAR_LENGTH
+ * constants for field BAR in register FOO.
+ */
+#define FIELD(reg, field, shift, length) \
+ enum { R_ ## reg ## _ ## field ## _SHIFT = (shift)}; \
+ enum { R_ ## reg ## _ ## field ## _LENGTH = (length)}; \
+ enum { R_ ## reg ## _ ## field ## _MASK = \
+ MAKE_64BIT_MASK(shift, length);
+
+/* Extract a field from a register */
+#define FIELD_EX32(storage, reg, field) \
+ extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH)
+
+/* Extract a field from an array of registers */
+#define ARRAY_FIELD_EX32(regs, reg, field) \
+ FIELD_EX32((regs)[R_ ## reg], reg, field)
+
+/* Deposit a register field. */
+#define FIELD_DP32(storage, reg, field, val) ({ \
+ struct { \
+ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
+ } v = { .v = val }; \
+ uint32_t d; \
+ d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH, v.v); \
+ d; })
+
+/* Deposit a field to array of registers. */
+#define ARRAY_FIELD_DP32(regs, reg, field, val) \
+ (regs)[R_ ## reg] = FIELD_DP32((regs)[R_ ## reg], reg, field, val);
+
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH v7 05/12] register: QOMify
2016-06-22 20:23 [Qemu-devel] [PATCH v7 00/12] data-driven device registers Alistair Francis
` (3 preceding siblings ...)
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 04/12] register: Define REG and FIELD macros Alistair Francis
@ 2016-06-22 20:23 ` Alistair Francis
2016-06-23 12:40 ` Peter Maydell
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 06/12] register: Add block initialise helper Alistair Francis
` (5 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Alistair Francis @ 2016-06-22 20:23 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: alistair.francis, crosthwaitepeter, edgar.iglesias,
edgar.iglesias, afaerber, fred.konrad, alex.bennee
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
QOMify registers as a child of TYPE_DEVICE. This allows registers to
define GPIOs.
Define an init helper that will do QOM initialisation.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
V7:
- Remove uneeded struct
- Fixup documentation
V5:
- Convert to using only one memory region
hw/core/register.c | 23 +++++++++++++++++++++++
include/hw/register.h | 16 ++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/hw/core/register.c b/hw/core/register.c
index 149aebb..41c11c8 100644
--- a/hw/core/register.c
+++ b/hw/core/register.c
@@ -155,6 +155,17 @@ void register_reset(RegisterInfo *reg)
register_write_val(reg, reg->access->reset);
}
+void register_init(RegisterInfo *reg)
+{
+ assert(reg);
+
+ if (!reg->data || !reg->access) {
+ return;
+ }
+
+ object_initialize((void *)reg, sizeof(*reg), TYPE_REGISTER);
+}
+
void register_write_memory(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
@@ -212,3 +223,15 @@ uint64_t register_read_memory(void *opaque, hwaddr addr,
return extract64(read_val, 0, size * 8);
}
+
+static const TypeInfo register_info = {
+ .name = TYPE_REGISTER,
+ .parent = TYPE_DEVICE,
+};
+
+static void register_register_types(void)
+{
+ type_register_static(®ister_info);
+}
+
+type_init(register_register_types)
diff --git a/include/hw/register.h b/include/hw/register.h
index 216b679..18a63df 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -11,6 +11,7 @@
#ifndef REGISTER_H
#define REGISTER_H
+#include "hw/qdev-core.h"
#include "exec/memory.h"
typedef struct RegisterInfo RegisterInfo;
@@ -72,6 +73,9 @@ struct RegisterAccessInfo {
*/
struct RegisterInfo {
+ /* <private> */
+ DeviceState parent_obj;
+
/* <public> */
void *data;
int data_size;
@@ -81,6 +85,9 @@ struct RegisterInfo {
void *opaque;
};
+#define TYPE_REGISTER "qemu,register"
+#define REGISTER(obj) OBJECT_CHECK(RegisterInfo, (obj), TYPE_REGISTER)
+
/**
* This structure is used to group all of the individual registers which are
* modeled using the RegisterInfo strucutre.
@@ -130,6 +137,15 @@ uint64_t register_read(RegisterInfo *reg, const char* prefix, bool debug);
void register_reset(RegisterInfo *reg);
/**
+ * Initialize a register. This will also setup any GPIO links which are used
+ * to connect register updates in one device to other devices. Generally this
+ * is useful for interrupt propagation.
+ * @reg: Register to initialize
+ */
+
+void register_init(RegisterInfo *reg);
+
+/**
* Memory API MMIO write handler that will write to a Register API register.
* @opaque: RegisterInfo to write to
* @addr: Address to write
--
2.7.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH v7 06/12] register: Add block initialise helper
2016-06-22 20:23 [Qemu-devel] [PATCH v7 00/12] data-driven device registers Alistair Francis
` (4 preceding siblings ...)
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 05/12] register: QOMify Alistair Francis
@ 2016-06-22 20:23 ` Alistair Francis
2016-06-23 12:55 ` Peter Maydell
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 07/12] dma: Add Xilinx Zynq devcfg device model Alistair Francis
` (4 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Alistair Francis @ 2016-06-22 20:23 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: alistair.francis, crosthwaitepeter, edgar.iglesias,
edgar.iglesias, afaerber, fred.konrad, alex.bennee
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Add a helper that will scan a static RegisterAccessInfo Array
and populate a container MemoryRegion with registers as defined.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
The reason that I'm not using GArray is because the array needs to store
the memory region that covers all of the registers.
V7:
- Return the memory region instead of adding it as a subregion
V6:
- Fixup the loop logic
V5:
- Convert to only using one memory region
V3:
- Fix typo
V2:
- Use memory_region_add_subregion_no_print()
hw/core/register.c | 36 ++++++++++++++++++++++++++++++++++++
include/hw/register.h | 24 ++++++++++++++++++++++++
2 files changed, 60 insertions(+)
diff --git a/hw/core/register.c b/hw/core/register.c
index 41c11c8..f32faac 100644
--- a/hw/core/register.c
+++ b/hw/core/register.c
@@ -224,6 +224,42 @@ uint64_t register_read_memory(void *opaque, hwaddr addr,
return extract64(read_val, 0, size * 8);
}
+MemoryRegion *register_init_block32(DeviceState *owner,
+ const RegisterAccessInfo *rae,
+ int num, RegisterInfo *ri, uint32_t *data,
+ const MemoryRegionOps *ops,
+ bool debug_enabled, uint64_t memory_size)
+{
+ const char *device_prefix = object_get_typename(OBJECT(owner));
+ RegisterInfoArray *r_array = g_malloc(sizeof(RegisterInfoArray));
+ int i;
+
+ r_array->r = g_malloc_n(num, sizeof(RegisterInfo *));
+ r_array->num_elements = num;
+ r_array->debug = debug_enabled;
+ r_array->prefix = device_prefix;
+
+ for (i = 0; i < num; i++) {
+ int index = rae[i].addr / 4;
+ RegisterInfo *r = &ri[index];
+
+ *r = (RegisterInfo) {
+ .data = &data[index],
+ .data_size = sizeof(uint32_t),
+ .access = &rae[i],
+ .opaque = owner,
+ };
+ register_init(r);
+
+ r_array->r[i] = r;
+ }
+
+ memory_region_init_io(&r_array->mem, OBJECT(owner), ops, r_array,
+ device_prefix, memory_size);
+
+ return &r_array->mem;
+}
+
static const TypeInfo register_info = {
.name = TYPE_REGISTER,
.parent = TYPE_DEVICE,
diff --git a/include/hw/register.h b/include/hw/register.h
index 18a63df..104d381 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -100,6 +100,8 @@ struct RegisterInfo {
*/
struct RegisterInfoArray {
+ MemoryRegion mem;
+
int num_elements;
RegisterInfo **r;
@@ -166,6 +168,28 @@ void register_write_memory(void *opaque, hwaddr addr, uint64_t value,
uint64_t register_read_memory(void *opaque, hwaddr addr, unsigned size);
+/**
+ * Init a block of registers into a container MemoryRegion. A
+ * number of constant register definitions are parsed to create a corresponding
+ * array of RegisterInfo's.
+ *
+ * @owner: device owning the registers
+ * @rae: Register definitions to init
+ * @num: number of registers to init (length of @rae)
+ * @ri: Register array to init
+ * @data: Array to use for register data
+ * @ops: Memory region ops to access registers.
+ * @debug enabled: turn on/off verbose debug information
+ * returns: A pointer to an initalised memory region that the caller should
+ * add to a container.
+ */
+
+MemoryRegion *register_init_block32(DeviceState *owner,
+ const RegisterAccessInfo *rae,
+ int num, RegisterInfo *ri, uint32_t *data,
+ const MemoryRegionOps *ops,
+ bool debug_enabled, uint64_t memory_size);
+
/* Define constants for a 32 bit register */
/* This macro will define A_FOO, for the byte address of a register
--
2.7.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH v7 07/12] dma: Add Xilinx Zynq devcfg device model
2016-06-22 20:23 [Qemu-devel] [PATCH v7 00/12] data-driven device registers Alistair Francis
` (5 preceding siblings ...)
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 06/12] register: Add block initialise helper Alistair Francis
@ 2016-06-22 20:24 ` Alistair Francis
2016-06-23 13:08 ` Peter Maydell
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 08/12] xilinx_zynq: Connect devcfg to the Zynq machine model Alistair Francis
` (3 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Alistair Francis @ 2016-06-22 20:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: alistair.francis, crosthwaitepeter, edgar.iglesias,
edgar.iglesias, afaerber, fred.konrad, alex.bennee
Add a minimal model for the devcfg device which is part of Zynq.
This model supports DMA capabilities and interrupt generation.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V7:
- Corrections to the internal device
V5:
- Corrections to the device model logic
default-configs/arm-softmmu.mak | 1 +
hw/dma/Makefile.objs | 1 +
hw/dma/xlnx-zynq-devcfg.c | 401 ++++++++++++++++++++++++++++++++++++++
include/hw/dma/xlnx-zynq-devcfg.h | 62 ++++++
include/hw/register.h | 2 +-
5 files changed, 466 insertions(+), 1 deletion(-)
create mode 100644 hw/dma/xlnx-zynq-devcfg.c
create mode 100644 include/hw/dma/xlnx-zynq-devcfg.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index c5bcba7..7a19863 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -66,6 +66,7 @@ CONFIG_PXA2XX=y
CONFIG_BITBANG_I2C=y
CONFIG_FRAMEBUFFER=y
CONFIG_XILINX_SPIPS=y
+CONFIG_ZYNQ_DEVCFG=y
CONFIG_ARM11SCU=y
CONFIG_A9SCU=y
diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs
index 8b0823e..087c8e6 100644
--- a/hw/dma/Makefile.objs
+++ b/hw/dma/Makefile.objs
@@ -5,6 +5,7 @@ common-obj-$(CONFIG_PL330) += pl330.o
common-obj-$(CONFIG_I82374) += i82374.o
common-obj-$(CONFIG_I8257) += i8257.o
common-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
+common-obj-$(CONFIG_ZYNQ_DEVCFG) += xlnx-zynq-devcfg.o
common-obj-$(CONFIG_ETRAXFS) += etraxfs_dma.o
common-obj-$(CONFIG_STP2000) += sparc32_dma.o
common-obj-$(CONFIG_SUN4M) += sun4m_iommu.o
diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c
new file mode 100644
index 0000000..bfb7ae6
--- /dev/null
+++ b/hw/dma/xlnx-zynq-devcfg.c
@@ -0,0 +1,401 @@
+/*
+ * QEMU model of the Xilinx Zynq Devcfg Interface
+ *
+ * (C) 2011 PetaLogix Pty Ltd
+ * (C) 2014 Xilinx Inc.
+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/dma/xlnx-zynq-devcfg.h"
+#include "qemu/bitops.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/dma.h"
+#include "qemu/log.h"
+
+#define FREQ_HZ 900000000
+
+#define BTT_MAX 0x400
+
+#ifndef XLNX_ZYNQ_DEVCFG_ERR_DEBUG
+#define XLNX_ZYNQ_DEVCFG_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT(fmt, args...) do { \
+ if (XLNX_ZYNQ_DEVCFG_ERR_DEBUG) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0);
+
+REG32(CTRL, 0x00)
+ FIELD(CTRL, FORCE_RST, 31, 1) /* Not supported, wr ignored */
+ FIELD(CTRL, PCAP_PR, 27, 1) /* Forced to 0 on bad unlock */
+ FIELD(CTRL, PCAP_MODE, 26, 1)
+ FIELD(CTRL, MULTIBOOT_EN, 24, 1)
+ FIELD(CTRL, USER_MODE, 15, 1)
+ FIELD(CTRL, PCFG_AES_FUSE, 12, 1)
+ FIELD(CTRL, PCFG_AES_EN, 9, 3)
+ FIELD(CTRL, SEU_EN, 8, 1)
+ FIELD(CTRL, SEC_EN, 7, 1)
+ FIELD(CTRL, SPNIDEN, 6, 1)
+ FIELD(CTRL, SPIDEN, 5, 1)
+ FIELD(CTRL, NIDEN, 4, 1)
+ FIELD(CTRL, DBGEN, 3, 1)
+ FIELD(CTRL, DAP_EN, 0, 3)
+
+REG32(LOCK, 0x04)
+ #define AES_FUSE_LOCK 4
+ #define AES_EN_LOCK 3
+ #define SEU_LOCK 2
+ #define SEC_LOCK 1
+ #define DBG_LOCK 0
+
+/* mapping bits in R_LOCK to what they lock in R_CTRL */
+static const uint32_t lock_ctrl_map[] = {
+ [AES_FUSE_LOCK] = R_CTRL_PCFG_AES_FUSE_MASK,
+ [AES_EN_LOCK] = R_CTRL_PCFG_AES_EN_MASK,
+ [SEU_LOCK] = R_CTRL_SEU_EN_MASK,
+ [SEC_LOCK] = R_CTRL_SEC_EN_MASK,
+ [DBG_LOCK] = R_CTRL_SPNIDEN_MASK | R_CTRL_SPIDEN_MASK |
+ R_CTRL_NIDEN_MASK | R_CTRL_DBGEN_MASK |
+ R_CTRL_DAP_EN_MASK,
+};
+
+REG32(CFG, 0x08)
+ FIELD(CFG, RFIFO_TH, 10, 2)
+ FIELD(CFG, WFIFO_TH, 8, 2)
+ FIELD(CFG, RCLK_EDGE, 7, 1)
+ FIELD(CFG, WCLK_EDGE, 6, 1)
+ FIELD(CFG, DISABLE_SRC_INC, 5, 1)
+ FIELD(CFG, DISABLE_DST_INC, 4, 1)
+#define R_CFG_RESET 0x50B
+
+REG32(INT_STS, 0x0C)
+ FIELD(INT_STS, PSS_GTS_USR_B, 31, 1)
+ FIELD(INT_STS, PSS_FST_CFG_B, 30, 1)
+ FIELD(INT_STS, PSS_CFG_RESET_B, 27, 1)
+ FIELD(INT_STS, RX_FIFO_OV, 18, 1)
+ FIELD(INT_STS, WR_FIFO_LVL, 17, 1)
+ FIELD(INT_STS, RD_FIFO_LVL, 16, 1)
+ FIELD(INT_STS, DMA_CMD_ERR, 15, 1)
+ FIELD(INT_STS, DMA_Q_OV, 14, 1)
+ FIELD(INT_STS, DMA_DONE, 13, 1)
+ FIELD(INT_STS, DMA_P_DONE, 12, 1)
+ FIELD(INT_STS, P2D_LEN_ERR, 11, 1)
+ FIELD(INT_STS, PCFG_DONE, 2, 1)
+ #define R_INT_STS_RSVD ((0x7 << 24) | (0x1 << 19) | (0xF < 7))
+
+REG32(INT_MASK, 0x10)
+
+REG32(STATUS, 0x14)
+ FIELD(STATUS, DMA_CMD_Q_F, 31, 1)
+ FIELD(STATUS, DMA_CMD_Q_E, 30, 1)
+ FIELD(STATUS, DMA_DONE_CNT, 28, 2)
+ FIELD(STATUS, RX_FIFO_LVL, 20, 5)
+ FIELD(STATUS, TX_FIFO_LVL, 12, 7)
+ FIELD(STATUS, PSS_GTS_USR_B, 11, 1)
+ FIELD(STATUS, PSS_FST_CFG_B, 10, 1)
+ FIELD(STATUS, PSS_CFG_RESET_B, 5, 1)
+
+REG32(DMA_SRC_ADDR, 0x18)
+REG32(DMA_DST_ADDR, 0x1C)
+REG32(DMA_SRC_LEN, 0x20)
+REG32(DMA_DST_LEN, 0x24)
+REG32(ROM_SHADOW, 0x28)
+REG32(SW_ID, 0x30)
+REG32(UNLOCK, 0x34)
+
+#define R_UNLOCK_MAGIC 0x757BDF0D
+
+REG32(MCTRL, 0x80)
+ FIELD(MCTRL, PS_VERSION, 28, 4)
+ FIELD(MCTRL, PCFG_POR_B, 8, 1)
+ FIELD(MCTRL, INT_PCAP_LPBK, 4, 1)
+ FIELD(MCTRL, QEMU, 3, 1)
+
+static void xlnx_zynq_devcfg_update_ixr(XlnxZynqDevcfg *s)
+{
+ qemu_set_irq(s->irq, ~s->regs[R_INT_MASK] & s->regs[R_INT_STS]);
+}
+
+static void xlnx_zynq_devcfg_reset(DeviceState *dev)
+{
+ XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(dev);
+ int i;
+
+ for (i = 0; i < XLNX_ZYNQ_DEVCFG_R_MAX; ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+}
+
+static void xlnx_zynq_devcfg_dma_go(XlnxZynqDevcfg *s)
+{
+ do {
+ uint8_t buf[BTT_MAX];
+ XlnxZynqDevcfgDMACmd *dmah = s->dma_cmd_fifo;
+ uint32_t btt = BTT_MAX;
+ bool loopback = s->regs[R_MCTRL] & R_MCTRL_INT_PCAP_LPBK_MASK;
+
+ btt = MIN(btt, dmah->src_len);
+ if (loopback) {
+ btt = MIN(btt, dmah->dest_len);
+ }
+ DB_PRINT("reading %x bytes from %x\n", btt, dmah->src_addr);
+ dma_memory_read(&address_space_memory, dmah->src_addr, buf, btt);
+ dmah->src_len -= btt;
+ dmah->src_addr += btt;
+ if (loopback && (dmah->src_len || dmah->dest_len)) {
+ DB_PRINT("writing %x bytes from %x\n", btt, dmah->dest_addr);
+ dma_memory_write(&address_space_memory, dmah->dest_addr, buf, btt);
+ dmah->dest_len -= btt;
+ dmah->dest_addr += btt;
+ }
+ if (!dmah->src_len && !dmah->dest_len) {
+ DB_PRINT("dma operation finished\n");
+ s->regs[R_INT_STS] |= R_INT_STS_DMA_DONE_MASK |
+ R_INT_STS_DMA_P_DONE_MASK;
+ s->dma_cmd_fifo_num--;
+ memmove(s->dma_cmd_fifo, &s->dma_cmd_fifo[1],
+ sizeof(s->dma_cmd_fifo));
+ }
+ xlnx_zynq_devcfg_update_ixr(s);
+ } while (s->dma_cmd_fifo_num);
+}
+
+static void r_ixr_post_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
+
+ xlnx_zynq_devcfg_update_ixr(s);
+}
+
+static uint64_t r_ctrl_pre_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(lock_ctrl_map); ++i) {
+ if (s->regs[R_LOCK] & 1 << i) {
+ val &= ~lock_ctrl_map[i];
+ val |= lock_ctrl_map[i] & s->regs[R_CTRL];
+ }
+ }
+ return val;
+}
+
+static void r_ctrl_post_write(RegisterInfo *reg, uint64_t val)
+{
+ const char *device_prefix = object_get_typename(OBJECT(reg->opaque));
+ uint32_t aes_en = FIELD_EX32(val, CTRL, PCFG_AES_EN);
+
+ if (aes_en != 0 && aes_en != 7) {
+ qemu_log_mask(LOG_UNIMP, "%s: warning, aes-en bits inconsistent,"
+ "unimplemented security reset should happen!\n",
+ device_prefix);
+ }
+}
+
+static void r_unlock_post_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
+ const char *device_prefix = object_get_typename(OBJECT(s));
+
+ if (val == R_UNLOCK_MAGIC) {
+ DB_PRINT("successful unlock\n");
+ /* BootROM will have already done the actual unlock so no need to do
+ * anything in successful subsequent unlock
+ */
+ } else { /* bad unlock attempt */
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: failed unlock\n", device_prefix);
+ s->regs[R_CTRL] &= ~R_CTRL_PCAP_PR_MASK;
+ s->regs[R_CTRL] &= ~R_CTRL_PCFG_AES_EN_MASK;
+ /* core becomes inaccessible */
+ memory_region_set_enabled(&s->iomem, false);
+ }
+}
+
+static uint64_t r_lock_pre_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
+
+ /* once bits are locked they stay locked */
+ return s->regs[R_LOCK] | val;
+}
+
+static void r_dma_dst_len_post_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
+
+ s->dma_cmd_fifo[s->dma_cmd_fifo_num] = (XlnxZynqDevcfgDMACmd) {
+ .src_addr = s->regs[R_DMA_SRC_ADDR] & ~0x3UL,
+ .dest_addr = s->regs[R_DMA_DST_ADDR] & ~0x3UL,
+ .src_len = s->regs[R_DMA_SRC_LEN] << 2,
+ .dest_len = s->regs[R_DMA_DST_LEN] << 2,
+ };
+ s->dma_cmd_fifo_num++;
+ DB_PRINT("dma transfer started; %d total transfers pending\n",
+ s->dma_cmd_fifo_num);
+ xlnx_zynq_devcfg_dma_go(s);
+}
+
+static const RegisterAccessInfo xlnx_zynq_devcfg_regs_info[] = {
+ { .name = "CTRL", .addr = A_CTRL,
+ .reset = R_CTRL_PCAP_PR_MASK | R_CTRL_PCAP_MODE_MASK | 0x3 << 13,
+ .rsvd = 0x1 << 28 | 0x3ff << 13 | 0x3 << 13,
+ .pre_write = r_ctrl_pre_write,
+ .post_write = r_ctrl_post_write,
+ },
+ { .name = "LOCK", .addr = A_LOCK,
+ .rsvd = MAKE_64BIT_MASK(5, 64 - 5),
+ .pre_write = r_lock_pre_write,
+ },
+ { .name = "CFG", .addr = A_CFG,
+ .reset = 1 << R_CFG_RFIFO_TH_SHIFT | 1 << R_CFG_WFIFO_TH_SHIFT | 0x8,
+ .rsvd = 0xfffff00f,
+ },
+ { .name = "INT_STS", .addr = A_INT_STS,
+ .w1c = ~R_INT_STS_RSVD,
+ .reset = R_INT_STS_PSS_GTS_USR_B_MASK |
+ R_INT_STS_PSS_CFG_RESET_B_MASK |
+ R_INT_STS_WR_FIFO_LVL_MASK,
+ .rsvd = R_INT_STS_RSVD,
+ .post_write = r_ixr_post_write,
+ },
+ { .name = "INT_MASK", .addr = A_INT_MASK,
+ .reset = ~0,
+ .rsvd = R_INT_STS_RSVD,
+ .post_write = r_ixr_post_write,
+ },
+ { .name = "STATUS", .addr = A_STATUS,
+ .reset = R_STATUS_DMA_CMD_Q_E_MASK |
+ R_STATUS_PSS_GTS_USR_B_MASK |
+ R_STATUS_PSS_CFG_RESET_B_MASK,
+ .ro = ~0,
+ },
+ { .name = "DMA_SRC_ADDR", .addr = A_DMA_SRC_ADDR, },
+ { .name = "DMA_DST_ADDR", .addr = A_DMA_DST_ADDR, },
+ { .name = "DMA_SRC_LEN", .addr = A_DMA_SRC_LEN,
+ .ro = MAKE_64BIT_MASK(27, 64 - 27) },
+ { .name = "DMA_DST_LEN", .addr = A_DMA_DST_LEN,
+ .ro = MAKE_64BIT_MASK(27, 64 - 27),
+ .post_write = r_dma_dst_len_post_write,
+ },
+ { .name = "ROM_SHADOW", .addr = A_ROM_SHADOW,
+ .rsvd = ~0ull,
+ },
+ { .name = "SW_ID", .addr = A_SW_ID, },
+ { .name = "UNLOCK", .addr = A_UNLOCK,
+ .post_write = r_unlock_post_write,
+ },
+ { .name = "MCTRL", .addr = R_MCTRL * 4,
+ /* Silicon 3.0 for version field, the mysterious reserved bit 23
+ * and QEMU platform identifier.
+ */
+ .reset = 0x2 << R_MCTRL_PS_VERSION_SHIFT | 1 << 23 | R_MCTRL_QEMU_MASK,
+ .ro = ~R_MCTRL_INT_PCAP_LPBK_MASK,
+ .rsvd = 0x00f00303,
+ },
+};
+
+static const MemoryRegionOps xlnx_zynq_devcfg_reg_ops = {
+ .read = register_read_memory,
+ .write = register_write_memory,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
+static const VMStateDescription vmstate_xlnx_zynq_devcfg_dma_cmd = {
+ .name = "xlnx_zynq_devcfg_dma_cmd",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(src_addr, XlnxZynqDevcfgDMACmd),
+ VMSTATE_UINT32(dest_addr, XlnxZynqDevcfgDMACmd),
+ VMSTATE_UINT32(src_len, XlnxZynqDevcfgDMACmd),
+ VMSTATE_UINT32(dest_len, XlnxZynqDevcfgDMACmd),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_xlnx_zynq_devcfg = {
+ .name = "xlnx_zynq_devcfg",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_ARRAY(dma_cmd_fifo, XlnxZynqDevcfg,
+ XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN, 0,
+ vmstate_xlnx_zynq_devcfg_dma_cmd,
+ XlnxZynqDevcfgDMACmd),
+ VMSTATE_UINT8(dma_cmd_fifo_num, XlnxZynqDevcfg),
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqDevcfg, XLNX_ZYNQ_DEVCFG_R_MAX),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void xlnx_zynq_devcfg_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(obj);
+ MemoryRegion *base_mem;
+
+ sysbus_init_irq(sbd, &s->irq);
+
+ memory_region_init(&s->iomem, obj, "devcfg", XLNX_ZYNQ_DEVCFG_R_MAX * 4);
+ base_mem =
+ register_init_block32(DEVICE(obj), xlnx_zynq_devcfg_regs_info,
+ ARRAY_SIZE(xlnx_zynq_devcfg_regs_info),
+ s->regs_info, s->regs,
+ &xlnx_zynq_devcfg_reg_ops,
+ XLNX_ZYNQ_DEVCFG_ERR_DEBUG,
+ XLNX_ZYNQ_DEVCFG_R_MAX);
+ memory_region_add_subregion(&s->iomem,
+ A_CTRL,
+ base_mem);
+
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void xlnx_zynq_devcfg_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = xlnx_zynq_devcfg_reset;
+ dc->vmsd = &vmstate_xlnx_zynq_devcfg;
+}
+
+static const TypeInfo xlnx_zynq_devcfg_info = {
+ .name = TYPE_XLNX_ZYNQ_DEVCFG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxZynqDevcfg),
+ .instance_init = xlnx_zynq_devcfg_init,
+ .class_init = xlnx_zynq_devcfg_class_init,
+};
+
+static void xlnx_zynq_devcfg_register_types(void)
+{
+ type_register_static(&xlnx_zynq_devcfg_info);
+}
+
+type_init(xlnx_zynq_devcfg_register_types)
diff --git a/include/hw/dma/xlnx-zynq-devcfg.h b/include/hw/dma/xlnx-zynq-devcfg.h
new file mode 100644
index 0000000..d40e5c8
--- /dev/null
+++ b/include/hw/dma/xlnx-zynq-devcfg.h
@@ -0,0 +1,62 @@
+/*
+ * QEMU model of the Xilinx Devcfg Interface
+ *
+ * (C) 2011 PetaLogix Pty Ltd
+ * (C) 2014 Xilinx Inc.
+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef XLNX_ZYNQ_DEVCFG_H
+
+#include "hw/register.h"
+#include "hw/sysbus.h"
+
+#define TYPE_XLNX_ZYNQ_DEVCFG "xlnx.ps7-dev-cfg"
+
+#define XLNX_ZYNQ_DEVCFG(obj) \
+ OBJECT_CHECK(XlnxZynqDevcfg, (obj), TYPE_XLNX_ZYNQ_DEVCFG)
+
+#define XLNX_ZYNQ_DEVCFG_R_MAX 0x118
+
+#define XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN 10
+
+typedef struct XlnxZynqDevcfgDMACmd {
+ uint32_t src_addr;
+ uint32_t dest_addr;
+ uint32_t src_len;
+ uint32_t dest_len;
+} XlnxZynqDevcfgDMACmd;
+
+typedef struct XlnxZynqDevcfg {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+ qemu_irq irq;
+
+ XlnxZynqDevcfgDMACmd dma_cmd_fifo[XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN];
+ uint8_t dma_cmd_fifo_num;
+
+ uint32_t regs[XLNX_ZYNQ_DEVCFG_R_MAX];
+ RegisterInfo regs_info[XLNX_ZYNQ_DEVCFG_R_MAX];
+} XlnxZynqDevcfg;
+
+#define XLNX_ZYNQ_DEVCFG_H
+#endif
diff --git a/include/hw/register.h b/include/hw/register.h
index 104d381..3e4d1ae 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -208,7 +208,7 @@ MemoryRegion *register_init_block32(DeviceState *owner,
enum { R_ ## reg ## _ ## field ## _SHIFT = (shift)}; \
enum { R_ ## reg ## _ ## field ## _LENGTH = (length)}; \
enum { R_ ## reg ## _ ## field ## _MASK = \
- MAKE_64BIT_MASK(shift, length);
+ MAKE_64BIT_MASK(shift, length)};
/* Extract a field from a register */
#define FIELD_EX32(storage, reg, field) \
--
2.7.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH v7 08/12] xilinx_zynq: Connect devcfg to the Zynq machine model
2016-06-22 20:23 [Qemu-devel] [PATCH v7 00/12] data-driven device registers Alistair Francis
` (6 preceding siblings ...)
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 07/12] dma: Add Xilinx Zynq devcfg device model Alistair Francis
@ 2016-06-22 20:24 ` Alistair Francis
2016-06-23 13:09 ` Peter Maydell
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 09/12] irq: Add opaque setter routine Alistair Francis
` (2 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Alistair Francis @ 2016-06-22 20:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: alistair.francis, crosthwaitepeter, edgar.iglesias,
edgar.iglesias, afaerber, fred.konrad, alex.bennee
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V7:
- Remove unused property add
V4:
- Small corrections to the device model logic
hw/arm/xilinx_zynq.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index aefebcf..f26c273 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -294,6 +294,12 @@ static void zynq_init(MachineState *machine)
sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
}
+ dev = qdev_create(NULL, "xlnx.ps7-dev-cfg");
+ qdev_init_nofail(dev);
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
+ sysbus_mmio_map(busdev, 0, 0xF8007000);
+
zynq_binfo.ram_size = ram_size;
zynq_binfo.kernel_filename = kernel_filename;
zynq_binfo.kernel_cmdline = kernel_cmdline;
--
2.7.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH v7 09/12] irq: Add opaque setter routine
2016-06-22 20:23 [Qemu-devel] [PATCH v7 00/12] data-driven device registers Alistair Francis
` (7 preceding siblings ...)
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 08/12] xilinx_zynq: Connect devcfg to the Zynq machine model Alistair Francis
@ 2016-06-22 20:24 ` Alistair Francis
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 10/12] register: Add GPIO API Alistair Francis
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 11/12] misc: Introduce ZynqMP IOU SLCR Alistair Francis
10 siblings, 0 replies; 27+ messages in thread
From: Alistair Francis @ 2016-06-22 20:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: alistair.francis, crosthwaitepeter, edgar.iglesias,
edgar.iglesias, afaerber, fred.konrad, alex.bennee
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Add a routine to set or override the opaque data of an IRQ.
Qdev currently always initialises IRQ opaque as the device itself.
This allows you to override to a custom opaque in the case where
there is extra or different data needed.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/core/irq.c | 5 +++++
include/hw/irq.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/hw/core/irq.c b/hw/core/irq.c
index 49ff2e6..9d125fb 100644
--- a/hw/core/irq.c
+++ b/hw/core/irq.c
@@ -77,6 +77,11 @@ qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n)
return irq;
}
+void qemu_irq_set_opaque(qemu_irq irq, void *opaque)
+{
+ irq->opaque = opaque;
+}
+
void qemu_free_irqs(qemu_irq *s, int n)
{
int i;
diff --git a/include/hw/irq.h b/include/hw/irq.h
index 4c4c2ea..edad0fc 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -44,6 +44,8 @@ qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n);
qemu_irq *qemu_extend_irqs(qemu_irq *old, int n_old, qemu_irq_handler handler,
void *opaque, int n);
+void qemu_irq_set_opaque(qemu_irq irq, void *opaque);
+
void qemu_free_irqs(qemu_irq *s, int n);
void qemu_free_irq(qemu_irq irq);
--
2.7.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH v7 10/12] register: Add GPIO API
2016-06-22 20:23 [Qemu-devel] [PATCH v7 00/12] data-driven device registers Alistair Francis
` (8 preceding siblings ...)
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 09/12] irq: Add opaque setter routine Alistair Francis
@ 2016-06-22 20:24 ` Alistair Francis
2016-06-23 13:19 ` Peter Maydell
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 11/12] misc: Introduce ZynqMP IOU SLCR Alistair Francis
10 siblings, 1 reply; 27+ messages in thread
From: Alistair Francis @ 2016-06-22 20:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: alistair.francis, crosthwaitepeter, edgar.iglesias,
edgar.iglesias, afaerber, fred.konrad, alex.bennee
Add GPIO functionality to the register API. This allows association
and automatic connection of GPIOs to bits in registers. GPIO inputs
will attach to handlers that automatically set read-only bits in
registers. GPIO outputs will be updated to reflect their field value
when their respective registers are written (or reset). Supports
active low GPIOs.
This is particularly effective for implementing system level
controllers, where heterogenous collections of control signals are
placed is a SoC specific peripheral then propagated all over the
system.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
[ EI Changes:
* register: Add a polarity field to GPIO connections
Makes it possible to directly connect active low signals
to generic interrupt pins.
]
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V6:
- Don't use qdev_pass_all_gpios() as it doesn't seem to work
V5
- Remove RegisterAccessError struct
hw/core/register.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/register.h | 27 ++++++++++++++
2 files changed, 124 insertions(+)
diff --git a/hw/core/register.c b/hw/core/register.c
index f32faac..476c5db 100644
--- a/hw/core/register.c
+++ b/hw/core/register.c
@@ -108,6 +108,7 @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t we,
}
register_write_val(reg, new_val);
+ register_refresh_gpios(reg, old_val, debug);
if (ac->post_write) {
ac->post_write(reg, new_val);
@@ -147,23 +148,119 @@ uint64_t register_read(RegisterInfo *reg, const char* prefix, bool debug)
void register_reset(RegisterInfo *reg)
{
g_assert(reg);
+ uint64_t old_val;
if (!reg->data || !reg->access) {
return;
}
+ old_val = register_read_val(reg);
+
register_write_val(reg, reg->access->reset);
+ register_refresh_gpios(reg, old_val, false);
+}
+
+void register_refresh_gpios(RegisterInfo *reg, uint64_t old_value, bool debug)
+{
+ const RegisterAccessInfo *ac;
+ const RegisterGPIOMapping *gpio;
+
+ ac = reg->access;
+ for (gpio = ac->gpios; gpio && gpio->name; gpio++) {
+ int i;
+
+ if (gpio->input) {
+ continue;
+ }
+
+ for (i = 0; i < gpio->num; ++i) {
+ uint64_t gpio_value, gpio_value_old;
+
+ qemu_irq gpo = qdev_get_gpio_out_connector(DEVICE(reg),
+ gpio->name, i);
+ gpio_value_old = extract64(old_value,
+ gpio->bit_pos + i * gpio->width,
+ gpio->width) ^ gpio->polarity;
+ gpio_value = extract64(register_read_val(reg),
+ gpio->bit_pos + i * gpio->width,
+ gpio->width) ^ gpio->polarity;
+ if (!(gpio_value_old ^ gpio_value)) {
+ continue;
+ }
+ if (debug && gpo) {
+ qemu_log("refreshing gpio out %s to %" PRIx64 "\n",
+ gpio->name, gpio_value);
+ }
+ qemu_set_irq(gpo, gpio_value);
+ }
+ }
+}
+
+typedef struct DeviceNamedGPIOHandlerOpaque {
+ DeviceState *dev;
+ const char *name;
+} DeviceNamedGPIOHandlerOpaque;
+
+static void register_gpio_handler(void *opaque, int n, int level)
+{
+ DeviceNamedGPIOHandlerOpaque *gho = opaque;
+ RegisterInfo *reg = REGISTER(gho->dev);
+
+ const RegisterAccessInfo *ac;
+ const RegisterGPIOMapping *gpio;
+
+ ac = reg->access;
+ for (gpio = ac->gpios; gpio && gpio->name; gpio++) {
+ if (gpio->input && !strcmp(gho->name, gpio->name)) {
+ register_write_val(reg, deposit64(register_read_val(reg),
+ gpio->bit_pos + n * gpio->width,
+ gpio->width,
+ level ^ gpio->polarity));
+ return;
+ }
+ }
+
+ abort();
}
void register_init(RegisterInfo *reg)
{
assert(reg);
+ const RegisterAccessInfo *ac;
+ const RegisterGPIOMapping *gpio;
if (!reg->data || !reg->access) {
return;
}
object_initialize((void *)reg, sizeof(*reg), TYPE_REGISTER);
+
+ ac = reg->access;
+ for (gpio = ac->gpios; gpio && gpio->name; gpio++) {
+ if (!gpio->num) {
+ ((RegisterGPIOMapping *)gpio)->num = 1;
+ }
+ if (!gpio->width) {
+ ((RegisterGPIOMapping *)gpio)->width = 1;
+ }
+ if (gpio->input) {
+ DeviceNamedGPIOHandlerOpaque gho = {
+ .name = gpio->name,
+ .dev = DEVICE(reg),
+ };
+ qemu_irq irq;
+
+ qdev_init_gpio_in_named(DEVICE(reg), register_gpio_handler,
+ gpio->name, gpio->num);
+ irq = qdev_get_gpio_in_named(DEVICE(reg), gpio->name, gpio->num);
+ qemu_irq_set_opaque(irq, g_memdup(&gho, sizeof(gho)));
+ } else {
+ qemu_irq *gpos = g_new0(qemu_irq, gpio->num);
+
+ qdev_init_gpio_out_named(DEVICE(reg), gpos, gpio->name, gpio->num);
+ qdev_pass_gpios(DEVICE(reg), reg->opaque, gpio->name);
+ }
+ }
}
void register_write_memory(void *opaque, hwaddr addr,
diff --git a/include/hw/register.h b/include/hw/register.h
index 3e4d1ae..112ca7b 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -13,11 +13,24 @@
#include "hw/qdev-core.h"
#include "exec/memory.h"
+#include "hw/irq.h"
typedef struct RegisterInfo RegisterInfo;
typedef struct RegisterAccessInfo RegisterAccessInfo;
typedef struct RegisterInfoArray RegisterInfoArray;
+#define REG_GPIO_POL_HIGH 0
+#define REG_GPIO_POL_LOW 1
+
+typedef struct RegisterGPIOMapping {
+ const char *name;
+ uint8_t bit_pos;
+ bool input;
+ bool polarity;
+ uint8_t num;
+ uint8_t width;
+} RegisterGPIOMapping;
+
/**
* Access description for a register that is part of guest accessible device
* state.
@@ -55,6 +68,8 @@ struct RegisterAccessInfo {
uint64_t (*post_read)(RegisterInfo *reg, uint64_t val);
hwaddr addr;
+
+ const RegisterGPIOMapping *gpios;
};
/**
@@ -148,6 +163,18 @@ void register_reset(RegisterInfo *reg);
void register_init(RegisterInfo *reg);
/**
+ * Refresh GPIO outputs based on diff between old value register current value.
+ * GPIOs are refreshed for fields where the old value differs to the current
+ * value.
+ *
+ * @reg: Register to refresh GPIO outs
+ * @old_value: previous value of register
+ * @debug: Should the read operation debug information be printed?
+ */
+
+void register_refresh_gpios(RegisterInfo *reg, uint64_t old_value, bool debug);
+
+/**
* Memory API MMIO write handler that will write to a Register API register.
* @opaque: RegisterInfo to write to
* @addr: Address to write
--
2.7.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH v7 11/12] misc: Introduce ZynqMP IOU SLCR
2016-06-22 20:23 [Qemu-devel] [PATCH v7 00/12] data-driven device registers Alistair Francis
` (9 preceding siblings ...)
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 10/12] register: Add GPIO API Alistair Francis
@ 2016-06-22 20:24 ` Alistair Francis
10 siblings, 0 replies; 27+ messages in thread
From: Alistair Francis @ 2016-06-22 20:24 UTC (permalink / raw)
To: qemu-devel, peter.maydell
Cc: alistair.francis, crosthwaitepeter, edgar.iglesias,
edgar.iglesias, afaerber, fred.konrad, alex.bennee
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
IOU = I/O Unit
SLCR = System Level Control Registers
This IP is a misc collections of control registers that switch various
properties of system IPs. Currently the only thing implemented is the
SD_SLOTTYPE control (implemented as a GPIO output).
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/misc/Makefile.objs | 1 +
hw/misc/xlnx-zynqmp-iou-slcr.c | 122 +++++++++++++++++++++++++++++++++
include/hw/misc/xlnx-zynqmp-iou-slcr.h | 47 +++++++++++++
3 files changed, 170 insertions(+)
create mode 100644 hw/misc/xlnx-zynqmp-iou-slcr.c
create mode 100644 include/hw/misc/xlnx-zynqmp-iou-slcr.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index ffb49c1..892f7db 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -43,6 +43,7 @@ obj-$(CONFIG_RASPI) += bcm2835_property.o
obj-$(CONFIG_SLAVIO) += slavio_misc.o
obj-$(CONFIG_ZYNQ) += zynq_slcr.o
obj-$(CONFIG_ZYNQ) += zynq-xadc.o
+obj-$(CONFIG_ZYNQ) += xlnx-zynqmp-iou-slcr.o
obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
obj-$(CONFIG_MIPS_CPS) += mips_cpc.o
diff --git a/hw/misc/xlnx-zynqmp-iou-slcr.c b/hw/misc/xlnx-zynqmp-iou-slcr.c
new file mode 100644
index 0000000..3ef5711
--- /dev/null
+++ b/hw/misc/xlnx-zynqmp-iou-slcr.c
@@ -0,0 +1,122 @@
+/*
+ * Xilinx ZynqMP IOU System Level Control Registers (SLCR)
+ *
+ * Copyright (c) 2013 Xilinx Inc
+ * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/misc/xlnx-zynqmp-iou-slcr.h"
+
+#ifndef XLNX_ZYNQMP_IOU_SLCR_ERR_DEBUG
+#define XLNX_ZYNQMP_IOU_SLCR_ERR_DEBUG 0
+#endif
+
+REG32(SD_SLOTTYPE, 0x310)
+ #define R_SD_SLOTTYPE_RSVD 0xffff7ffe
+
+static const RegisterAccessInfo xlnx_zynqmp_iou_slcr_regs_info[] = {
+ { .name = "SD Slot TYPE", .addr = A_SD_SLOTTYPE,
+ .rsvd = R_SD_SLOTTYPE_RSVD,
+ .gpios = (RegisterGPIOMapping []) {
+ { .name = "SD0_SLOTTYPE", .bit_pos = 0 },
+ { .name = "SD1_SLOTTYPE", .bit_pos = 15 },
+ {},
+ }
+ }
+ /* FIXME: Complete device model */
+};
+
+static void xlnx_zynqmp_iou_slcr_reset(DeviceState *dev)
+{
+ XlnxZynqMPIOUSLCR *s = XLNX_ZYNQMP_IOU_SLCR(dev);
+ int i;
+
+ for (i = 0; i < XLNX_ZYNQ_MP_IOU_SLCR_R_MAX; ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+}
+
+static const MemoryRegionOps xlnx_zynqmp_iou_slcr_ops = {
+ .read = register_read_memory,
+ .write = register_write_memory,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
+static void xlnx_zynqmp_iou_slcr_init(Object *obj)
+{
+ XlnxZynqMPIOUSLCR *s = XLNX_ZYNQMP_IOU_SLCR(obj);
+ MemoryRegion *base_mem;
+
+ memory_region_init(&s->iomem, obj, "MMIO",
+ XLNX_ZYNQ_MP_IOU_SLCR_R_MAX * 4);
+ base_mem =
+ register_init_block32(DEVICE(obj), xlnx_zynqmp_iou_slcr_regs_info,
+ ARRAY_SIZE(xlnx_zynqmp_iou_slcr_regs_info),
+ s->regs_info, s->regs,
+ &xlnx_zynqmp_iou_slcr_ops,
+ XLNX_ZYNQMP_IOU_SLCR_ERR_DEBUG,
+ XLNX_ZYNQ_MP_IOU_SLCR_R_MAX);
+ memory_region_add_subregion(&s->iomem,
+ A_SD_SLOTTYPE,
+ base_mem);
+
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
+}
+
+static const VMStateDescription vmstate_xlnx_zynqmp_iou_slcr = {
+ .name = "xlnx_zynqmp_iou_slcr",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPIOUSLCR,
+ XLNX_ZYNQ_MP_IOU_SLCR_R_MAX),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void xlnx_zynqmp_iou_slcr_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = xlnx_zynqmp_iou_slcr_reset;
+ dc->vmsd = &vmstate_xlnx_zynqmp_iou_slcr;
+}
+
+static const TypeInfo xlnx_zynqmp_iou_slcr_info = {
+ .name = TYPE_XLNX_ZYNQMP_IOU_SLCR,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxZynqMPIOUSLCR),
+ .class_init = xlnx_zynqmp_iou_slcr_class_init,
+ .instance_init = xlnx_zynqmp_iou_slcr_init,
+};
+
+static void xlnx_zynqmp_iou_slcr_register_types(void)
+{
+ type_register_static(&xlnx_zynqmp_iou_slcr_info);
+}
+
+type_init(xlnx_zynqmp_iou_slcr_register_types)
diff --git a/include/hw/misc/xlnx-zynqmp-iou-slcr.h b/include/hw/misc/xlnx-zynqmp-iou-slcr.h
new file mode 100644
index 0000000..b3bcb19
--- /dev/null
+++ b/include/hw/misc/xlnx-zynqmp-iou-slcr.h
@@ -0,0 +1,47 @@
+/*
+ * Xilinx ZynqMP IOU system level control registers (SLCR)
+ *
+ * Copyright (c) 2013 Xilinx Inc
+ * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/register.h"
+
+#define TYPE_XLNX_ZYNQMP_IOU_SLCR "xlnx_zynqmp-iou-slcr"
+
+#define XLNX_ZYNQMP_IOU_SLCR(obj) \
+ OBJECT_CHECK(XlnxZynqMPIOUSLCR, (obj), TYPE_XLNX_ZYNQMP_IOU_SLCR)
+
+#define XLNX_ZYNQ_MP_IOU_SLCR_R_MAX (0x314 / 4)
+
+typedef struct XlnxZynqMPIOUSLCR XlnxZynqMPIOUSLCR;
+
+struct XlnxZynqMPIOUSLCR {
+ /*< private >*/
+ SysBusDevice busdev;
+
+ /*< public >*/
+ MemoryRegion iomem;
+
+ uint32_t regs[XLNX_ZYNQ_MP_IOU_SLCR_R_MAX];
+ RegisterInfo regs_info[XLNX_ZYNQ_MP_IOU_SLCR_R_MAX];
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH v7 01/12] bitops: Add MAKE_64BIT_MASK macro
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 01/12] bitops: Add MAKE_64BIT_MASK macro Alistair Francis
@ 2016-06-23 12:14 ` Peter Maydell
0 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2016-06-23 12:14 UTC (permalink / raw)
To: Alistair Francis
Cc: QEMU Developers, Peter Crosthwaite, Edgar Iglesias,
Edgar E. Iglesias, Andreas Färber, KONRAD Frédéric,
Alex Bennée
On 22 June 2016 at 21:23, Alistair Francis <alistair.francis@xilinx.com> wrote:
> Add a macro that creates a 64bit value which has length number of ones
> shifted across by the value of shift.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH v7 03/12] register: Add Memory API glue
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 03/12] register: Add Memory API glue Alistair Francis
@ 2016-06-23 12:21 ` Peter Maydell
2016-06-23 16:30 ` Alistair Francis
0 siblings, 1 reply; 27+ messages in thread
From: Peter Maydell @ 2016-06-23 12:21 UTC (permalink / raw)
To: Alistair Francis
Cc: QEMU Developers, Peter Crosthwaite, Edgar Iglesias,
Edgar E. Iglesias, Andreas Färber, KONRAD Frédéric,
Alex Bennée
On 22 June 2016 at 21:23, Alistair Francis <alistair.francis@xilinx.com> wrote:
> Add memory io handlers that glue the register API to the memory API.
> Just translation functions at this stage. Although it does allow for
> devices to be created without all-in-one mmio r/w handlers.
>
> This patch also adds the RegisterInfoArray struct, which allows all of
> the individual RegisterInfo structs to be grouped into a single memory
> region.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> V7:
> - Remove endianess handling
> - Remove assert() and log missing registers
> V6:
> - Add the memory region later
> V5:
> - Convert to using only one memory region
>
> hw/core/register.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/register.h | 43 ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 101 insertions(+)
>
> diff --git a/hw/core/register.c b/hw/core/register.c
> index cc067f1..149aebb 100644
> --- a/hw/core/register.c
> +++ b/hw/core/register.c
> @@ -154,3 +154,61 @@ void register_reset(RegisterInfo *reg)
>
> register_write_val(reg, reg->access->reset);
> }
> +
> +void register_write_memory(void *opaque, hwaddr addr,
> + uint64_t value, unsigned size)
> +{
> + RegisterInfoArray *reg_array = opaque;
> + RegisterInfo *reg = NULL;
> + uint64_t we = ~0;
Really ~0 and not ~0ULL ? In any case this shouldn't need
initializing as we will always set it later.
> + int i;
> +
> + for (i = 0; i < reg_array->num_elements; i++) {
> + if (reg_array->r[i]->access->addr == addr) {
> + reg = reg_array->r[i];
> + break;
> + }
> + }
> +
> + if (!reg) {
> + qemu_log_mask(LOG_UNIMP, "Write to unimplemented register at " \
> + "address: %#" PRIx64 "\n", addr);
Shouldn't this be a LOG_GUEST_ERROR ?
> + return;
> + }
> +
> + /* Generate appropriate write enable mask */
> + if (reg->data_size < size) {
> + we = MAKE_64BIT_MASK(0, reg->data_size * 8);
> + } else if (reg->data_size >= size) {
Why not just "else {" ?
> + we = MAKE_64BIT_MASK(0, size * 8);
> + }
> +
> + register_write(reg, value, we, reg_array->prefix,
> + reg_array->debug);
> +}
> +
> +uint64_t register_read_memory(void *opaque, hwaddr addr,
> + unsigned size)
> +{
> + RegisterInfoArray *reg_array = opaque;
> + RegisterInfo *reg = NULL;
> + uint64_t read_val;
> + int i;
> +
> + for (i = 0; i < reg_array->num_elements; i++) {
> + if (reg_array->r[i]->access->addr == addr) {
> + reg = reg_array->r[i];
> + break;
> + }
> + }
> +
> + if (!reg) {
> + qemu_log_mask(LOG_UNIMP, "Read to unimplemented register at " \
> + "address: %#" PRIx64 "\n", addr);
> + return 0;
> + }
> +
> + read_val = register_read(reg, reg_array->prefix, reg_array->debug);
This will silently affect bits of the register outside the
specified size with clear-on-read or other "reads have
side effects" behaviour, which isn't consistent with how
we handle writes.
> /**
> + * This structure is used to group all of the individual registers which are
> + * modeled using the RegisterInfo strucutre.
"structure"
> + *
> + * @r is an aray containing of all the relevent RegisterInfo structures.
> + *
> + * @num_elements is the number of elements in the array r
> + *
> + * @mem: optional Memory region for the register
> + */
> +
> +struct RegisterInfoArray {
> + int num_elements;
> + RegisterInfo **r;
> +
> + bool debug;
> + const char *prefix;
> +};
> +
thanks
-- PMM
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH v7 04/12] register: Define REG and FIELD macros
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 04/12] register: Define REG and FIELD macros Alistair Francis
@ 2016-06-23 12:39 ` Peter Maydell
2016-06-23 17:51 ` Alistair Francis
0 siblings, 1 reply; 27+ messages in thread
From: Peter Maydell @ 2016-06-23 12:39 UTC (permalink / raw)
To: Alistair Francis
Cc: QEMU Developers, Peter Crosthwaite, Edgar Iglesias,
Edgar E. Iglesias, Andreas Färber, KONRAD Frédéric,
Alex Bennée
On 22 June 2016 at 21:23, Alistair Francis <alistair.francis@xilinx.com> wrote:
> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>
> Define some macros that can be used for defining registers and fields.
>
> The REG32 macro will define A_FOO, for the byte address of a register
> as well as R_FOO for the uint32_t[] register number (A_FOO / 4).
>
> The FIELD macro will define FOO_BAR_MASK, FOO_BAR_SHIFT and
> FOO_BAR_LENGTH constants for field BAR in register FOO.
>
> Finally, there are some shorthand helpers for extracting/depositing
> fields from registers based on these naming schemes.
>
> Usage can greatly reduce the verbosity of device code.
>
> The deposit and extract macros (eg FIELD_EX32, FIELD_DP32 etc.) can be
> used to generate extract and deposits without any repetition of the name
> stems.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> [ EI Changes:
> * Add Deposit macros
> ]
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> diff --git a/include/hw/register.h b/include/hw/register.h
> index e160150..216b679 100644
> --- a/include/hw/register.h
> +++ b/include/hw/register.h
> @@ -150,4 +150,47 @@ void register_write_memory(void *opaque, hwaddr addr, uint64_t value,
>
> uint64_t register_read_memory(void *opaque, hwaddr addr, unsigned size);
>
> +/* Define constants for a 32 bit register */
> +
> +/* This macro will define A_FOO, for the byte address of a register
> + * as well as R_FOO for the uint32_t[] register number (A_FOO / 4).
> + */
> +#define REG32(reg, addr) \
> + enum { A_ ## reg = (addr) }; \
> + enum { R_ ## reg = (addr) / 4 };
> +
> +/* Define SHIFT, LEGTH and MASK constants for a field within a register */
> +
"LENGTH".
> +/* Deposit a register field. */
> +#define FIELD_DP32(storage, reg, field, val) ({ \
> + struct { \
> + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
> + } v = { .v = val }; \
> + uint32_t d; \
> + d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
> + R_ ## reg ## _ ## field ## _LENGTH, v.v); \
> + d; })
If you insist on different semantics to deposit32() (which I
still think is a bad idea), can we at least have a comment
noting the difference?
(Do you get a warning for putting a signed negative value into
a field?)
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH v7 05/12] register: QOMify
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 05/12] register: QOMify Alistair Francis
@ 2016-06-23 12:40 ` Peter Maydell
0 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2016-06-23 12:40 UTC (permalink / raw)
To: Alistair Francis
Cc: QEMU Developers, Peter Crosthwaite, Edgar Iglesias,
Edgar E. Iglesias, Andreas Färber, KONRAD Frédéric,
Alex Bennée
On 22 June 2016 at 21:23, Alistair Francis <alistair.francis@xilinx.com> wrote:
> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>
> QOMify registers as a child of TYPE_DEVICE. This allows registers to
> define GPIOs.
>
> Define an init helper that will do QOM initialisation.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> Reviewed-by: KONRAD Frederic <fred.konrad@greensocs.com>
> ---
> V7:
> - Remove uneeded struct
> - Fixup documentation
> V5:
> - Convert to using only one memory region
>
> hw/core/register.c | 23 +++++++++++++++++++++++
> include/hw/register.h | 16 ++++++++++++++++
> 2 files changed, 39 insertions(+)
>
> diff --git a/hw/core/register.c b/hw/core/register.c
> index 149aebb..41c11c8 100644
> --- a/hw/core/register.c
> +++ b/hw/core/register.c
> @@ -155,6 +155,17 @@ void register_reset(RegisterInfo *reg)
> register_write_val(reg, reg->access->reset);
> }
>
> +void register_init(RegisterInfo *reg)
> +{
> + assert(reg);
> +
> + if (!reg->data || !reg->access) {
> + return;
> + }
> +
> + object_initialize((void *)reg, sizeof(*reg), TYPE_REGISTER);
> +}
> +
> void register_write_memory(void *opaque, hwaddr addr,
> uint64_t value, unsigned size)
> {
> @@ -212,3 +223,15 @@ uint64_t register_read_memory(void *opaque, hwaddr addr,
>
> return extract64(read_val, 0, size * 8);
> }
> +
> +static const TypeInfo register_info = {
> + .name = TYPE_REGISTER,
> + .parent = TYPE_DEVICE,
> +};
> +
> +static void register_register_types(void)
> +{
> + type_register_static(®ister_info);
> +}
> +
> +type_init(register_register_types)
> diff --git a/include/hw/register.h b/include/hw/register.h
> index 216b679..18a63df 100644
> --- a/include/hw/register.h
> +++ b/include/hw/register.h
> @@ -11,6 +11,7 @@
> #ifndef REGISTER_H
> #define REGISTER_H
>
> +#include "hw/qdev-core.h"
> #include "exec/memory.h"
>
> typedef struct RegisterInfo RegisterInfo;
> @@ -72,6 +73,9 @@ struct RegisterAccessInfo {
> */
>
> struct RegisterInfo {
> + /* <private> */
> + DeviceState parent_obj;
> +
> /* <public> */
> void *data;
> int data_size;
> @@ -81,6 +85,9 @@ struct RegisterInfo {
> void *opaque;
> };
>
> +#define TYPE_REGISTER "qemu,register"
> +#define REGISTER(obj) OBJECT_CHECK(RegisterInfo, (obj), TYPE_REGISTER)
> +
> /**
> * This structure is used to group all of the individual registers which are
> * modeled using the RegisterInfo strucutre.
> @@ -130,6 +137,15 @@ uint64_t register_read(RegisterInfo *reg, const char* prefix, bool debug);
> void register_reset(RegisterInfo *reg);
>
> /**
> + * Initialize a register. This will also setup any GPIO links which are used
> + * to connect register updates in one device to other devices. Generally this
> + * is useful for interrupt propagation.
> + * @reg: Register to initialize
> + */
Leave the remark about GPIOs to the patch that adds GPIO support.
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH v7 06/12] register: Add block initialise helper
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 06/12] register: Add block initialise helper Alistair Francis
@ 2016-06-23 12:55 ` Peter Maydell
2016-06-23 17:29 ` Alistair Francis
0 siblings, 1 reply; 27+ messages in thread
From: Peter Maydell @ 2016-06-23 12:55 UTC (permalink / raw)
To: Alistair Francis
Cc: QEMU Developers, Peter Crosthwaite, Edgar Iglesias,
Edgar E. Iglesias, Andreas Färber, KONRAD Frédéric,
Alex Bennée
On 22 June 2016 at 21:23, Alistair Francis <alistair.francis@xilinx.com> wrote:
> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>
> Add a helper that will scan a static RegisterAccessInfo Array
> and populate a container MemoryRegion with registers as defined.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> The reason that I'm not using GArray is because the array needs to store
> the memory region that covers all of the registers.
>
> V7:
> - Return the memory region instead of adding it as a subregion
> V6:
> - Fixup the loop logic
> V5:
> - Convert to only using one memory region
> V3:
> - Fix typo
> V2:
> - Use memory_region_add_subregion_no_print()
>
> hw/core/register.c | 36 ++++++++++++++++++++++++++++++++++++
> include/hw/register.h | 24 ++++++++++++++++++++++++
> 2 files changed, 60 insertions(+)
>
> diff --git a/hw/core/register.c b/hw/core/register.c
> index 41c11c8..f32faac 100644
> --- a/hw/core/register.c
> +++ b/hw/core/register.c
> @@ -224,6 +224,42 @@ uint64_t register_read_memory(void *opaque, hwaddr addr,
> return extract64(read_val, 0, size * 8);
> }
>
> +MemoryRegion *register_init_block32(DeviceState *owner,
> + const RegisterAccessInfo *rae,
> + int num, RegisterInfo *ri, uint32_t *data,
> + const MemoryRegionOps *ops,
> + bool debug_enabled, uint64_t memory_size)
> +{
> + const char *device_prefix = object_get_typename(OBJECT(owner));
> + RegisterInfoArray *r_array = g_malloc(sizeof(RegisterInfoArray));
Prefer g_new0(RegisterInfoArray, 1)
> + int i;
> +
> + r_array->r = g_malloc_n(num, sizeof(RegisterInfo *));
Prefer g_new0(RegisterInfo *, num)
> + r_array->num_elements = num;
> + r_array->debug = debug_enabled;
> + r_array->prefix = device_prefix;
> +
> + for (i = 0; i < num; i++) {
> + int index = rae[i].addr / 4;
> + RegisterInfo *r = &ri[index];
> +
> + *r = (RegisterInfo) {
> + .data = &data[index],
> + .data_size = sizeof(uint32_t),
> + .access = &rae[i],
> + .opaque = owner,
> + };
> + register_init(r);
> +
> + r_array->r[i] = r;
> + }
> +
> + memory_region_init_io(&r_array->mem, OBJECT(owner), ops, r_array,
> + device_prefix, memory_size);
> +
> + return &r_array->mem;
This API doesn't seem to have any provision for being able to
free the RegisterInfoArray later ? (Consider hotpluggable devices
which need to be able to free everything on hot-unplug.)
> +
> static const TypeInfo register_info = {
> .name = TYPE_REGISTER,
> .parent = TYPE_DEVICE,
> diff --git a/include/hw/register.h b/include/hw/register.h
> index 18a63df..104d381 100644
> --- a/include/hw/register.h
> +++ b/include/hw/register.h
> @@ -100,6 +100,8 @@ struct RegisterInfo {
> */
>
> struct RegisterInfoArray {
> + MemoryRegion mem;
> +
> int num_elements;
> RegisterInfo **r;
>
> @@ -166,6 +168,28 @@ void register_write_memory(void *opaque, hwaddr addr, uint64_t value,
>
> uint64_t register_read_memory(void *opaque, hwaddr addr, unsigned size);
>
> +/**
> + * Init a block of registers into a container MemoryRegion. A
> + * number of constant register definitions are parsed to create a corresponding
> + * array of RegisterInfo's.
> + *
> + * @owner: device owning the registers
> + * @rae: Register definitions to init
> + * @num: number of registers to init (length of @rae)
> + * @ri: Register array to init
> + * @data: Array to use for register data
> + * @ops: Memory region ops to access registers.
> + * @debug enabled: turn on/off verbose debug information
It's not clear to me which of these are input arguments to the
function, and which are things that the function initializes
(I think 'ri' is purely output?)
> + * returns: A pointer to an initalised memory region that the caller should
"initialized"
> + * add to a container.
> + */
> +
> +MemoryRegion *register_init_block32(DeviceState *owner,
> + const RegisterAccessInfo *rae,
> + int num, RegisterInfo *ri, uint32_t *data,
> + const MemoryRegionOps *ops,
> + bool debug_enabled, uint64_t memory_size);
> +
> /* Define constants for a 32 bit register */
>
> /* This macro will define A_FOO, for the byte address of a register
> --
> 2.7.4
thanks
-- PMM
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH v7 07/12] dma: Add Xilinx Zynq devcfg device model
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 07/12] dma: Add Xilinx Zynq devcfg device model Alistair Francis
@ 2016-06-23 13:08 ` Peter Maydell
2016-06-23 18:08 ` Alistair Francis
0 siblings, 1 reply; 27+ messages in thread
From: Peter Maydell @ 2016-06-23 13:08 UTC (permalink / raw)
To: Alistair Francis
Cc: QEMU Developers, Peter Crosthwaite, Edgar Iglesias,
Edgar E. Iglesias, Andreas Färber, KONRAD Frédéric,
Alex Bennée
On 22 June 2016 at 21:24, Alistair Francis <alistair.francis@xilinx.com> wrote:
> Add a minimal model for the devcfg device which is part of Zynq.
> This model supports DMA capabilities and interrupt generation.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> + if (!dmah->src_len && !dmah->dest_len) {
> + DB_PRINT("dma operation finished\n");
> + s->regs[R_INT_STS] |= R_INT_STS_DMA_DONE_MASK |
> + R_INT_STS_DMA_P_DONE_MASK;
> + s->dma_cmd_fifo_num--;
> + memmove(s->dma_cmd_fifo, &s->dma_cmd_fifo[1],
> + sizeof(s->dma_cmd_fifo));
This looks like an off-by-one error in the size argument.
> + }
> + xlnx_zynq_devcfg_update_ixr(s);
> + } while (s->dma_cmd_fifo_num);
> +}
> +static void r_unlock_post_write(RegisterInfo *reg, uint64_t val)
> +{
> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
> + const char *device_prefix = object_get_typename(OBJECT(s));
> +
> + if (val == R_UNLOCK_MAGIC) {
> + DB_PRINT("successful unlock\n");
> + /* BootROM will have already done the actual unlock so no need to do
> + * anything in successful subsequent unlock
> + */
I don't understand this comment. Shouldn't we be marking the
memory region as enabled here, to handle the case of
"guest locks the device via a bad-unlock-attempt; guest
unlocks via a good unlock attempt" ? What the guest bootrom
does or doesn't do isn't usually relevant to the device
implementation.
> + } else { /* bad unlock attempt */
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: failed unlock\n", device_prefix);
> + s->regs[R_CTRL] &= ~R_CTRL_PCAP_PR_MASK;
> + s->regs[R_CTRL] &= ~R_CTRL_PCFG_AES_EN_MASK;
> + /* core becomes inaccessible */
> + memory_region_set_enabled(&s->iomem, false);
> + }
> +}
> +
> +static const RegisterAccessInfo xlnx_zynq_devcfg_regs_info[] = {
> + { .name = "CTRL", .addr = A_CTRL,
> + .reset = R_CTRL_PCAP_PR_MASK | R_CTRL_PCAP_MODE_MASK | 0x3 << 13,
> + .rsvd = 0x1 << 28 | 0x3ff << 13 | 0x3 << 13,
> + .pre_write = r_ctrl_pre_write,
> + .post_write = r_ctrl_post_write,
> + },
> + { .name = "LOCK", .addr = A_LOCK,
> + .rsvd = MAKE_64BIT_MASK(5, 64 - 5),
> + .pre_write = r_lock_pre_write,
> + },
> + { .name = "CFG", .addr = A_CFG,
> + .reset = 1 << R_CFG_RFIFO_TH_SHIFT | 1 << R_CFG_WFIFO_TH_SHIFT | 0x8,
I was expecting this to use the R_CFG_RESET value defined earlier
(or alternatively don't bother defining a #define for it...)
> +static const VMStateDescription vmstate_xlnx_zynq_devcfg = {
> + .name = "xlnx_zynq_devcfg",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
You don't need an _old field.
> + .fields = (VMStateField[]) {
> + VMSTATE_STRUCT_ARRAY(dma_cmd_fifo, XlnxZynqDevcfg,
> + XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN, 0,
> + vmstate_xlnx_zynq_devcfg_dma_cmd,
> + XlnxZynqDevcfgDMACmd),
> + VMSTATE_UINT8(dma_cmd_fifo_num, XlnxZynqDevcfg),
> + VMSTATE_UINT32_ARRAY(regs, XlnxZynqDevcfg, XLNX_ZYNQ_DEVCFG_R_MAX),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> diff --git a/include/hw/register.h b/include/hw/register.h
> index 104d381..3e4d1ae 100644
> --- a/include/hw/register.h
> +++ b/include/hw/register.h
> @@ -208,7 +208,7 @@ MemoryRegion *register_init_block32(DeviceState *owner,
> enum { R_ ## reg ## _ ## field ## _SHIFT = (shift)}; \
> enum { R_ ## reg ## _ ## field ## _LENGTH = (length)}; \
> enum { R_ ## reg ## _ ## field ## _MASK = \
> - MAKE_64BIT_MASK(shift, length);
> + MAKE_64BIT_MASK(shift, length)};
>
> /* Extract a field from a register */
> #define FIELD_EX32(storage, reg, field) \
Should this hunk be in some earlier patch ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH v7 08/12] xilinx_zynq: Connect devcfg to the Zynq machine model
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 08/12] xilinx_zynq: Connect devcfg to the Zynq machine model Alistair Francis
@ 2016-06-23 13:09 ` Peter Maydell
0 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2016-06-23 13:09 UTC (permalink / raw)
To: Alistair Francis
Cc: QEMU Developers, Peter Crosthwaite, Edgar Iglesias,
Edgar E. Iglesias, Andreas Färber, KONRAD Frédéric,
Alex Bennée
On 22 June 2016 at 21:24, Alistair Francis <alistair.francis@xilinx.com> wrote:
> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> V7:
> - Remove unused property add
> V4:
> - Small corrections to the device model logic
>
> hw/arm/xilinx_zynq.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
> index aefebcf..f26c273 100644
> --- a/hw/arm/xilinx_zynq.c
> +++ b/hw/arm/xilinx_zynq.c
> @@ -294,6 +294,12 @@ static void zynq_init(MachineState *machine)
> sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
> }
>
> + dev = qdev_create(NULL, "xlnx.ps7-dev-cfg");
> + qdev_init_nofail(dev);
> + busdev = SYS_BUS_DEVICE(dev);
> + sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
> + sysbus_mmio_map(busdev, 0, 0xF8007000);
> +
> zynq_binfo.ram_size = ram_size;
> zynq_binfo.kernel_filename = kernel_filename;
> zynq_binfo.kernel_cmdline = kernel_cmdline;
> --
> 2.7.4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH v7 10/12] register: Add GPIO API
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 10/12] register: Add GPIO API Alistair Francis
@ 2016-06-23 13:19 ` Peter Maydell
2016-06-23 18:14 ` Alistair Francis
0 siblings, 1 reply; 27+ messages in thread
From: Peter Maydell @ 2016-06-23 13:19 UTC (permalink / raw)
To: Alistair Francis
Cc: QEMU Developers, Peter Crosthwaite, Edgar Iglesias,
Edgar E. Iglesias, Andreas Färber, KONRAD Frédéric,
Alex Bennée
On 22 June 2016 at 21:24, Alistair Francis <alistair.francis@xilinx.com> wrote:
> Add GPIO functionality to the register API. This allows association
> and automatic connection of GPIOs to bits in registers. GPIO inputs
> will attach to handlers that automatically set read-only bits in
> registers. GPIO outputs will be updated to reflect their field value
> when their respective registers are written (or reset). Supports
> active low GPIOs.
>
> This is particularly effective for implementing system level
> controllers, where heterogenous collections of control signals are
> placed is a SoC specific peripheral then propagated all over the
> system.
I still don't think this is a good idea. GPIOs are device-level,
not register-level. Most devices don't really have very many
GPIOs. It should be easy to wire up "change GPIO state based on
new register value" from a register post-write hook. This API
can't handle the absolute most common case, which is "GPIO state
is based on a bit being set in (raw-state-register AND mask-register)."
Basically I don't think GPIOs belong in this API, and I don't think
there's a good case that adding them makes a significant class
of devices much easier to write.
thanks
-- PMM
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH v7 03/12] register: Add Memory API glue
2016-06-23 12:21 ` Peter Maydell
@ 2016-06-23 16:30 ` Alistair Francis
0 siblings, 0 replies; 27+ messages in thread
From: Alistair Francis @ 2016-06-23 16:30 UTC (permalink / raw)
To: Peter Maydell
Cc: Alistair Francis, Edgar Iglesias, QEMU Developers,
Peter Crosthwaite, Edgar E. Iglesias, Alex Bennée,
Andreas Färber, KONRAD Frédéric
On Thu, Jun 23, 2016 at 5:21 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 22 June 2016 at 21:23, Alistair Francis <alistair.francis@xilinx.com> wrote:
>> Add memory io handlers that glue the register API to the memory API.
>> Just translation functions at this stage. Although it does allow for
>> devices to be created without all-in-one mmio r/w handlers.
>>
>> This patch also adds the RegisterInfoArray struct, which allows all of
>> the individual RegisterInfo structs to be grouped into a single memory
>> region.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>> V7:
>> - Remove endianess handling
>> - Remove assert() and log missing registers
>> V6:
>> - Add the memory region later
>> V5:
>> - Convert to using only one memory region
>>
>> hw/core/register.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++
>> include/hw/register.h | 43 ++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 101 insertions(+)
>>
>> diff --git a/hw/core/register.c b/hw/core/register.c
>> index cc067f1..149aebb 100644
>> --- a/hw/core/register.c
>> +++ b/hw/core/register.c
>> @@ -154,3 +154,61 @@ void register_reset(RegisterInfo *reg)
>>
>> register_write_val(reg, reg->access->reset);
>> }
>> +
>> +void register_write_memory(void *opaque, hwaddr addr,
>> + uint64_t value, unsigned size)
>> +{
>> + RegisterInfoArray *reg_array = opaque;
>> + RegisterInfo *reg = NULL;
>> + uint64_t we = ~0;
>
> Really ~0 and not ~0ULL ? In any case this shouldn't need
> initializing as we will always set it later.
>
>> + int i;
>> +
>> + for (i = 0; i < reg_array->num_elements; i++) {
>> + if (reg_array->r[i]->access->addr == addr) {
>> + reg = reg_array->r[i];
>> + break;
>> + }
>> + }
>> +
>> + if (!reg) {
>> + qemu_log_mask(LOG_UNIMP, "Write to unimplemented register at " \
>> + "address: %#" PRIx64 "\n", addr);
>
> Shouldn't this be a LOG_GUEST_ERROR ?
>
>> + return;
>> + }
>> +
>> + /* Generate appropriate write enable mask */
>> + if (reg->data_size < size) {
>> + we = MAKE_64BIT_MASK(0, reg->data_size * 8);
>> + } else if (reg->data_size >= size) {
>
> Why not just "else {" ?
>
>> + we = MAKE_64BIT_MASK(0, size * 8);
>> + }
>> +
>> + register_write(reg, value, we, reg_array->prefix,
>> + reg_array->debug);
>> +}
>> +
>> +uint64_t register_read_memory(void *opaque, hwaddr addr,
>> + unsigned size)
>> +{
>> + RegisterInfoArray *reg_array = opaque;
>> + RegisterInfo *reg = NULL;
>> + uint64_t read_val;
>> + int i;
>> +
>> + for (i = 0; i < reg_array->num_elements; i++) {
>> + if (reg_array->r[i]->access->addr == addr) {
>> + reg = reg_array->r[i];
>> + break;
>> + }
>> + }
>> +
>> + if (!reg) {
>> + qemu_log_mask(LOG_UNIMP, "Read to unimplemented register at " \
>> + "address: %#" PRIx64 "\n", addr);
>> + return 0;
>> + }
>> +
>> + read_val = register_read(reg, reg_array->prefix, reg_array->debug);
>
> This will silently affect bits of the register outside the
> specified size with clear-on-read or other "reads have
> side effects" behaviour, which isn't consistent with how
> we handle writes.
>
>> /**
>> + * This structure is used to group all of the individual registers which are
>> + * modeled using the RegisterInfo strucutre.
>
> "structure"
Fixed all.
Thanks,
Alistair
>
>> + *
>> + * @r is an aray containing of all the relevent RegisterInfo structures.
>> + *
>> + * @num_elements is the number of elements in the array r
>> + *
>> + * @mem: optional Memory region for the register
>> + */
>> +
>> +struct RegisterInfoArray {
>> + int num_elements;
>> + RegisterInfo **r;
>> +
>> + bool debug;
>> + const char *prefix;
>> +};
>> +
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH v7 06/12] register: Add block initialise helper
2016-06-23 12:55 ` Peter Maydell
@ 2016-06-23 17:29 ` Alistair Francis
2016-06-23 18:02 ` Peter Maydell
0 siblings, 1 reply; 27+ messages in thread
From: Alistair Francis @ 2016-06-23 17:29 UTC (permalink / raw)
To: Peter Maydell
Cc: Alistair Francis, Edgar Iglesias, QEMU Developers,
Peter Crosthwaite, Edgar E. Iglesias, Alex Bennée,
Andreas Färber, KONRAD Frédéric
On Thu, Jun 23, 2016 at 5:55 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 22 June 2016 at 21:23, Alistair Francis <alistair.francis@xilinx.com> wrote:
>> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>>
>> Add a helper that will scan a static RegisterAccessInfo Array
>> and populate a container MemoryRegion with registers as defined.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>> The reason that I'm not using GArray is because the array needs to store
>> the memory region that covers all of the registers.
>>
>> V7:
>> - Return the memory region instead of adding it as a subregion
>> V6:
>> - Fixup the loop logic
>> V5:
>> - Convert to only using one memory region
>> V3:
>> - Fix typo
>> V2:
>> - Use memory_region_add_subregion_no_print()
>>
>> hw/core/register.c | 36 ++++++++++++++++++++++++++++++++++++
>> include/hw/register.h | 24 ++++++++++++++++++++++++
>> 2 files changed, 60 insertions(+)
>>
>> diff --git a/hw/core/register.c b/hw/core/register.c
>> index 41c11c8..f32faac 100644
>> --- a/hw/core/register.c
>> +++ b/hw/core/register.c
>> @@ -224,6 +224,42 @@ uint64_t register_read_memory(void *opaque, hwaddr addr,
>> return extract64(read_val, 0, size * 8);
>> }
>>
>> +MemoryRegion *register_init_block32(DeviceState *owner,
>> + const RegisterAccessInfo *rae,
>> + int num, RegisterInfo *ri, uint32_t *data,
>> + const MemoryRegionOps *ops,
>> + bool debug_enabled, uint64_t memory_size)
>> +{
>> + const char *device_prefix = object_get_typename(OBJECT(owner));
>> + RegisterInfoArray *r_array = g_malloc(sizeof(RegisterInfoArray));
>
> Prefer g_new0(RegisterInfoArray, 1)
>
>> + int i;
>> +
>> + r_array->r = g_malloc_n(num, sizeof(RegisterInfo *));
>
> Prefer g_new0(RegisterInfo *, num)
Ok, I have fixed these.
>
>> + r_array->num_elements = num;
>> + r_array->debug = debug_enabled;
>> + r_array->prefix = device_prefix;
>> +
>> + for (i = 0; i < num; i++) {
>> + int index = rae[i].addr / 4;
>> + RegisterInfo *r = &ri[index];
>> +
>> + *r = (RegisterInfo) {
>> + .data = &data[index],
>> + .data_size = sizeof(uint32_t),
>> + .access = &rae[i],
>> + .opaque = owner,
>> + };
>> + register_init(r);
>> +
>> + r_array->r[i] = r;
>> + }
>> +
>> + memory_region_init_io(&r_array->mem, OBJECT(owner), ops, r_array,
>> + device_prefix, memory_size);
>> +
>> + return &r_array->mem;
>
> This API doesn't seem to have any provision for being able to
> free the RegisterInfoArray later ? (Consider hotpluggable devices
> which need to be able to free everything on hot-unplug.)
I have added a finalise function which can be used to free the register array.
This meant I had to change register_init_block32() to return
RegisterInfoArray instead of a MemoryRegion.
>> +
>> static const TypeInfo register_info = {
>> .name = TYPE_REGISTER,
>> .parent = TYPE_DEVICE,
>> diff --git a/include/hw/register.h b/include/hw/register.h
>> index 18a63df..104d381 100644
>> --- a/include/hw/register.h
>> +++ b/include/hw/register.h
>> @@ -100,6 +100,8 @@ struct RegisterInfo {
>> */
>>
>> struct RegisterInfoArray {
>> + MemoryRegion mem;
>> +
>> int num_elements;
>> RegisterInfo **r;
>>
>> @@ -166,6 +168,28 @@ void register_write_memory(void *opaque, hwaddr addr, uint64_t value,
>>
>> uint64_t register_read_memory(void *opaque, hwaddr addr, unsigned size);
>>
>> +/**
>> + * Init a block of registers into a container MemoryRegion. A
>> + * number of constant register definitions are parsed to create a corresponding
>> + * array of RegisterInfo's.
>> + *
>> + * @owner: device owning the registers
>> + * @rae: Register definitions to init
>> + * @num: number of registers to init (length of @rae)
>> + * @ri: Register array to init
>> + * @data: Array to use for register data
>> + * @ops: Memory region ops to access registers.
>> + * @debug enabled: turn on/off verbose debug information
>
> It's not clear to me which of these are input arguments to the
> function, and which are things that the function initializes
> (I think 'ri' is purely output?)
The function expects everything to already be initialised, it just
wires them up.
ri should already be allocated, this function just sets up some pointers to it.
I added a comment in the description saying that ri and data must
already be allocated. Is that enough?
>
>> + * returns: A pointer to an initalised memory region that the caller should
>
> "initialized"
Fixed.
Thanks,
Alistair
>
>> + * add to a container.
>> + */
>> +
>> +MemoryRegion *register_init_block32(DeviceState *owner,
>> + const RegisterAccessInfo *rae,
>> + int num, RegisterInfo *ri, uint32_t *data,
>> + const MemoryRegionOps *ops,
>> + bool debug_enabled, uint64_t memory_size);
>> +
>> /* Define constants for a 32 bit register */
>>
>> /* This macro will define A_FOO, for the byte address of a register
>> --
>> 2.7.4
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH v7 04/12] register: Define REG and FIELD macros
2016-06-23 12:39 ` Peter Maydell
@ 2016-06-23 17:51 ` Alistair Francis
0 siblings, 0 replies; 27+ messages in thread
From: Alistair Francis @ 2016-06-23 17:51 UTC (permalink / raw)
To: Peter Maydell
Cc: Alistair Francis, Edgar Iglesias, QEMU Developers,
Peter Crosthwaite, Edgar E. Iglesias, Alex Bennée,
Andreas Färber, KONRAD Frédéric
On Thu, Jun 23, 2016 at 5:39 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 22 June 2016 at 21:23, Alistair Francis <alistair.francis@xilinx.com> wrote:
>> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>>
>> Define some macros that can be used for defining registers and fields.
>>
>> The REG32 macro will define A_FOO, for the byte address of a register
>> as well as R_FOO for the uint32_t[] register number (A_FOO / 4).
>>
>> The FIELD macro will define FOO_BAR_MASK, FOO_BAR_SHIFT and
>> FOO_BAR_LENGTH constants for field BAR in register FOO.
>>
>> Finally, there are some shorthand helpers for extracting/depositing
>> fields from registers based on these naming schemes.
>>
>> Usage can greatly reduce the verbosity of device code.
>>
>> The deposit and extract macros (eg FIELD_EX32, FIELD_DP32 etc.) can be
>> used to generate extract and deposits without any repetition of the name
>> stems.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> [ EI Changes:
>> * Add Deposit macros
>> ]
>> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>
>> diff --git a/include/hw/register.h b/include/hw/register.h
>> index e160150..216b679 100644
>> --- a/include/hw/register.h
>> +++ b/include/hw/register.h
>> @@ -150,4 +150,47 @@ void register_write_memory(void *opaque, hwaddr addr, uint64_t value,
>>
>> uint64_t register_read_memory(void *opaque, hwaddr addr, unsigned size);
>>
>> +/* Define constants for a 32 bit register */
>> +
>> +/* This macro will define A_FOO, for the byte address of a register
>> + * as well as R_FOO for the uint32_t[] register number (A_FOO / 4).
>> + */
>> +#define REG32(reg, addr) \
>> + enum { A_ ## reg = (addr) }; \
>> + enum { R_ ## reg = (addr) / 4 };
>> +
>> +/* Define SHIFT, LEGTH and MASK constants for a field within a register */
>> +
>
> "LENGTH".
Fixed
>
>> +/* Deposit a register field. */
>> +#define FIELD_DP32(storage, reg, field, val) ({ \
>> + struct { \
>> + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
>> + } v = { .v = val }; \
>> + uint32_t d; \
>> + d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
>> + R_ ## reg ## _ ## field ## _LENGTH, v.v); \
>> + d; })
>
> If you insist on different semantics to deposit32() (which I
> still think is a bad idea), can we at least have a comment
> noting the difference?
I have added a comment.
>
> (Do you get a warning for putting a signed negative value into
> a field?)
No, I don't see any warnings for forcing negative values in.
Thanks,
Alistair
>
> Otherwise
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH v7 06/12] register: Add block initialise helper
2016-06-23 17:29 ` Alistair Francis
@ 2016-06-23 18:02 ` Peter Maydell
2016-06-23 18:10 ` Alistair Francis
0 siblings, 1 reply; 27+ messages in thread
From: Peter Maydell @ 2016-06-23 18:02 UTC (permalink / raw)
To: Alistair Francis
Cc: Edgar Iglesias, QEMU Developers, Peter Crosthwaite,
Edgar E. Iglesias, Alex Bennée, Andreas Färber,
KONRAD Frédéric
On 23 June 2016 at 18:29, Alistair Francis <alistair.francis@xilinx.com> wrote:
> On Thu, Jun 23, 2016 at 5:55 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
>> It's not clear to me which of these are input arguments to the
>> function, and which are things that the function initializes
>> (I think 'ri' is purely output?)
>
> The function expects everything to already be initialised, it just
> wires them up.
>
> ri should already be allocated, this function just sets up some pointers to it.
>
> I added a comment in the description saying that ri and data must
> already be allocated. Is that enough?
Does the caller have to initialize the array that ri points to
before it calls this?
thanks
-- PMM
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH v7 07/12] dma: Add Xilinx Zynq devcfg device model
2016-06-23 13:08 ` Peter Maydell
@ 2016-06-23 18:08 ` Alistair Francis
0 siblings, 0 replies; 27+ messages in thread
From: Alistair Francis @ 2016-06-23 18:08 UTC (permalink / raw)
To: Peter Maydell
Cc: Alistair Francis, Edgar Iglesias, QEMU Developers,
Peter Crosthwaite, Edgar E. Iglesias, Alex Bennée,
Andreas Färber, KONRAD Frédéric
On Thu, Jun 23, 2016 at 6:08 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 22 June 2016 at 21:24, Alistair Francis <alistair.francis@xilinx.com> wrote:
>> Add a minimal model for the devcfg device which is part of Zynq.
>> This model supports DMA capabilities and interrupt generation.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>
>> + if (!dmah->src_len && !dmah->dest_len) {
>> + DB_PRINT("dma operation finished\n");
>> + s->regs[R_INT_STS] |= R_INT_STS_DMA_DONE_MASK |
>> + R_INT_STS_DMA_P_DONE_MASK;
>> + s->dma_cmd_fifo_num--;
>> + memmove(s->dma_cmd_fifo, &s->dma_cmd_fifo[1],
>> + sizeof(s->dma_cmd_fifo));
>
> This looks like an off-by-one error in the size argument.
Fixed.
>
>> + }
>> + xlnx_zynq_devcfg_update_ixr(s);
>> + } while (s->dma_cmd_fifo_num);
>> +}
>
>> +static void r_unlock_post_write(RegisterInfo *reg, uint64_t val)
>> +{
>> + XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
>> + const char *device_prefix = object_get_typename(OBJECT(s));
>> +
>> + if (val == R_UNLOCK_MAGIC) {
>> + DB_PRINT("successful unlock\n");
>> + /* BootROM will have already done the actual unlock so no need to do
>> + * anything in successful subsequent unlock
>> + */
>
> I don't understand this comment. Shouldn't we be marking the
> memory region as enabled here, to handle the case of
> "guest locks the device via a bad-unlock-attempt; guest
> unlocks via a good unlock attempt" ? What the guest bootrom
> does or doesn't do isn't usually relevant to the device
> implementation.
Agreed. I have added the ability to unlock.
>
>> + } else { /* bad unlock attempt */
>> + qemu_log_mask(LOG_GUEST_ERROR, "%s: failed unlock\n", device_prefix);
>> + s->regs[R_CTRL] &= ~R_CTRL_PCAP_PR_MASK;
>> + s->regs[R_CTRL] &= ~R_CTRL_PCFG_AES_EN_MASK;
>> + /* core becomes inaccessible */
>> + memory_region_set_enabled(&s->iomem, false);
>> + }
>> +}
>
>> +
>> +static const RegisterAccessInfo xlnx_zynq_devcfg_regs_info[] = {
>> + { .name = "CTRL", .addr = A_CTRL,
>> + .reset = R_CTRL_PCAP_PR_MASK | R_CTRL_PCAP_MODE_MASK | 0x3 << 13,
>> + .rsvd = 0x1 << 28 | 0x3ff << 13 | 0x3 << 13,
>> + .pre_write = r_ctrl_pre_write,
>> + .post_write = r_ctrl_post_write,
>> + },
>> + { .name = "LOCK", .addr = A_LOCK,
>> + .rsvd = MAKE_64BIT_MASK(5, 64 - 5),
>> + .pre_write = r_lock_pre_write,
>> + },
>> + { .name = "CFG", .addr = A_CFG,
>> + .reset = 1 << R_CFG_RFIFO_TH_SHIFT | 1 << R_CFG_WFIFO_TH_SHIFT | 0x8,
>
> I was expecting this to use the R_CFG_RESET value defined earlier
> (or alternatively don't bother defining a #define for it...)
Fixed, it's now using the macro.
>
>
>> +static const VMStateDescription vmstate_xlnx_zynq_devcfg = {
>> + .name = "xlnx_zynq_devcfg",
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .minimum_version_id_old = 1,
>
> You don't need an _old field.
Removed.
>
>> + .fields = (VMStateField[]) {
>> + VMSTATE_STRUCT_ARRAY(dma_cmd_fifo, XlnxZynqDevcfg,
>> + XLNX_ZYNQ_DEVCFG_DMA_CMD_FIFO_LEN, 0,
>> + vmstate_xlnx_zynq_devcfg_dma_cmd,
>> + XlnxZynqDevcfgDMACmd),
>> + VMSTATE_UINT8(dma_cmd_fifo_num, XlnxZynqDevcfg),
>> + VMSTATE_UINT32_ARRAY(regs, XlnxZynqDevcfg, XLNX_ZYNQ_DEVCFG_R_MAX),
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>
>
>> diff --git a/include/hw/register.h b/include/hw/register.h
>> index 104d381..3e4d1ae 100644
>> --- a/include/hw/register.h
>> +++ b/include/hw/register.h
>> @@ -208,7 +208,7 @@ MemoryRegion *register_init_block32(DeviceState *owner,
>> enum { R_ ## reg ## _ ## field ## _SHIFT = (shift)}; \
>> enum { R_ ## reg ## _ ## field ## _LENGTH = (length)}; \
>> enum { R_ ## reg ## _ ## field ## _MASK = \
>> - MAKE_64BIT_MASK(shift, length);
>> + MAKE_64BIT_MASK(shift, length)};
>>
>> /* Extract a field from a register */
>> #define FIELD_EX32(storage, reg, field) \
>
> Should this hunk be in some earlier patch ?
Yes it should, I have fixed this as well.
Thanks,
Alistair
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH v7 06/12] register: Add block initialise helper
2016-06-23 18:02 ` Peter Maydell
@ 2016-06-23 18:10 ` Alistair Francis
0 siblings, 0 replies; 27+ messages in thread
From: Alistair Francis @ 2016-06-23 18:10 UTC (permalink / raw)
To: Peter Maydell
Cc: Alistair Francis, Edgar Iglesias, QEMU Developers,
Peter Crosthwaite, Edgar E. Iglesias, Alex Bennée,
Andreas Färber, KONRAD Frédéric
On Thu, Jun 23, 2016 at 11:02 AM, Peter Maydell
<peter.maydell@linaro.org> wrote:
> On 23 June 2016 at 18:29, Alistair Francis <alistair.francis@xilinx.com> wrote:
>> On Thu, Jun 23, 2016 at 5:55 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
>>> It's not clear to me which of these are input arguments to the
>>> function, and which are things that the function initializes
>>> (I think 'ri' is purely output?)
>>
>> The function expects everything to already be initialised, it just
>> wires them up.
>>
>> ri should already be allocated, this function just sets up some pointers to it.
>>
>> I added a comment in the description saying that ri and data must
>> already be allocated. Is that enough?
>
> Does the caller have to initialize the array that ri points to
> before it calls this?
All the caller has to do is ensure that the array exists and is large
enough for the number of registers.
Thanks,
Alistair
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH v7 10/12] register: Add GPIO API
2016-06-23 13:19 ` Peter Maydell
@ 2016-06-23 18:14 ` Alistair Francis
0 siblings, 0 replies; 27+ messages in thread
From: Alistair Francis @ 2016-06-23 18:14 UTC (permalink / raw)
To: Peter Maydell
Cc: Alistair Francis, Edgar Iglesias, QEMU Developers,
Peter Crosthwaite, Edgar E. Iglesias, Alex Bennée,
Andreas Färber, KONRAD Frédéric
On Thu, Jun 23, 2016 at 6:19 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 22 June 2016 at 21:24, Alistair Francis <alistair.francis@xilinx.com> wrote:
>> Add GPIO functionality to the register API. This allows association
>> and automatic connection of GPIOs to bits in registers. GPIO inputs
>> will attach to handlers that automatically set read-only bits in
>> registers. GPIO outputs will be updated to reflect their field value
>> when their respective registers are written (or reset). Supports
>> active low GPIOs.
>>
>> This is particularly effective for implementing system level
>> controllers, where heterogenous collections of control signals are
>> placed is a SoC specific peripheral then propagated all over the
>> system.
>
> I still don't think this is a good idea. GPIOs are device-level,
> not register-level. Most devices don't really have very many
> GPIOs. It should be easy to wire up "change GPIO state based on
> new register value" from a register post-write hook. This API
> can't handle the absolute most common case, which is "GPIO state
> is based on a bit being set in (raw-state-register AND mask-register)."
>
> Basically I don't think GPIOs belong in this API, and I don't think
> there's a good case that adding them makes a significant class
> of devices much easier to write.
Ok, I'm going to remove the GPIO part from this patch set (the last
few patches).
Once this patchset is accepted I'll spin up a new series with the
GPIOs and some better/more complex devices and we can go from there.
Thanks,
Alistair
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2016-06-23 18:15 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-06-22 20:23 [Qemu-devel] [PATCH v7 00/12] data-driven device registers Alistair Francis
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 01/12] bitops: Add MAKE_64BIT_MASK macro Alistair Francis
2016-06-23 12:14 ` Peter Maydell
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 02/12] register: Add Register API Alistair Francis
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 03/12] register: Add Memory API glue Alistair Francis
2016-06-23 12:21 ` Peter Maydell
2016-06-23 16:30 ` Alistair Francis
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 04/12] register: Define REG and FIELD macros Alistair Francis
2016-06-23 12:39 ` Peter Maydell
2016-06-23 17:51 ` Alistair Francis
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 05/12] register: QOMify Alistair Francis
2016-06-23 12:40 ` Peter Maydell
2016-06-22 20:23 ` [Qemu-devel] [PATCH v7 06/12] register: Add block initialise helper Alistair Francis
2016-06-23 12:55 ` Peter Maydell
2016-06-23 17:29 ` Alistair Francis
2016-06-23 18:02 ` Peter Maydell
2016-06-23 18:10 ` Alistair Francis
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 07/12] dma: Add Xilinx Zynq devcfg device model Alistair Francis
2016-06-23 13:08 ` Peter Maydell
2016-06-23 18:08 ` Alistair Francis
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 08/12] xilinx_zynq: Connect devcfg to the Zynq machine model Alistair Francis
2016-06-23 13:09 ` Peter Maydell
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 09/12] irq: Add opaque setter routine Alistair Francis
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 10/12] register: Add GPIO API Alistair Francis
2016-06-23 13:19 ` Peter Maydell
2016-06-23 18:14 ` Alistair Francis
2016-06-22 20:24 ` [Qemu-devel] [PATCH v7 11/12] misc: Introduce ZynqMP IOU SLCR Alistair Francis
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