From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com,
TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: Re: [PATCH v2 01/14] tcg/op-gvec: Fix iteration step in 32-bit operation
Date: Sun, 1 Sep 2024 09:59:13 +1000 [thread overview]
Message-ID: <6b3305c3-2f23-47d0-949e-a3e562f49cbb@linaro.org> (raw)
In-Reply-To: <20240830061607.1940-2-zhiwei_liu@linux.alibaba.com>
On 8/30/24 16:15, LIU Zhiwei wrote:
> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>
> The loop in the 32-bit case of the vector compare operation
> was incorrectly incrementing by 8 bytes per iteration instead
> of 4 bytes. This caused the function to process only half of
> the intended elements.
>
> Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
> Fixes: 9622c697d1 (tcg: Add gvec compare with immediate and scalar operand)
> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
> tcg/tcg-op-gvec.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
>
> diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
> index 0308732d9b..78ee1ced80 100644
> --- a/tcg/tcg-op-gvec.c
> +++ b/tcg/tcg-op-gvec.c
> @@ -3939,7 +3939,7 @@ void tcg_gen_gvec_cmps(TCGCond cond, unsigned vece, uint32_t dofs,
> uint32_t i;
>
> tcg_gen_extrl_i64_i32(t1, c);
> - for (i = 0; i < oprsz; i += 8) {
> + for (i = 0; i < oprsz; i += 4) {
> tcg_gen_ld_i32(t0, tcg_env, aofs + i);
> tcg_gen_negsetcond_i32(cond, t0, t0, t1);
> tcg_gen_st_i32(t0, tcg_env, dofs + i);
next prev parent reply other threads:[~2024-09-01 0:00 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-30 6:15 [PATCH v2 00/14] tcg/riscv: Add support for vector LIU Zhiwei
2024-08-30 6:15 ` [PATCH v2 01/14] tcg/op-gvec: Fix iteration step in 32-bit operation LIU Zhiwei
2024-08-31 23:59 ` Richard Henderson [this message]
2024-08-30 6:15 ` [PATCH v2 02/14] util: Add RISC-V vector extension probe in cpuinfo LIU Zhiwei
2024-09-02 0:12 ` Richard Henderson
2024-08-30 6:15 ` [PATCH v2 03/14] tcg/riscv: Add basic support for vector LIU Zhiwei
2024-09-02 0:28 ` Richard Henderson
2024-08-30 6:15 ` [PATCH v2 04/14] tcg/riscv: Add riscv vset{i}vli support LIU Zhiwei
2024-09-02 1:06 ` Richard Henderson
2024-08-30 6:15 ` [PATCH v2 05/14] tcg/riscv: Implement vector load/store LIU Zhiwei
2024-09-02 1:31 ` Richard Henderson
2024-08-30 6:15 ` [PATCH v2 06/14] tcg/riscv: Implement vector mov/dup{m/i} LIU Zhiwei
2024-09-02 1:36 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 07/14] tcg/riscv: Add support for basic vector opcodes LIU Zhiwei
2024-09-02 1:39 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 08/14] tcg/riscv: Implement vector cmp ops LIU Zhiwei
2024-09-03 6:45 ` Richard Henderson
2024-09-03 14:51 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 09/14] tcg/riscv: Implement vector neg ops LIU Zhiwei
2024-09-03 14:52 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 10/14] tcg/riscv: Implement vector sat/mul ops LIU Zhiwei
2024-09-03 14:52 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 11/14] tcg/riscv: Implement vector min/max ops LIU Zhiwei
2024-09-03 14:53 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 12/14] tcg/riscv: Implement vector shs/v ops LIU Zhiwei
2024-09-03 14:54 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 13/14] tcg/riscv: Implement vector roti/v/x shi ops LIU Zhiwei
2024-09-03 15:15 ` Richard Henderson
2024-09-04 15:25 ` LIU Zhiwei
2024-09-04 19:05 ` Richard Henderson
2024-09-05 1:40 ` LIU Zhiwei
2024-08-30 6:16 ` [PATCH v2 14/14] tcg/riscv: Enable native vector support for TCG host LIU Zhiwei
2024-09-03 15:02 ` Richard Henderson
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