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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3056f83ba71sm2191691a91.13.2025.04.02.11.46.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 02 Apr 2025 11:46:52 -0700 (PDT) Message-ID: <6b3e4490-781f-4337-837c-3ed38483332a@linaro.org> Date: Wed, 2 Apr 2025 11:46:51 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PULL 04/23] include/exec: Split out exec/cpu-interrupt.h To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Cc: Pierrick Bouvier , =?UTF-8?Q?Alex_Benn=C3=A9e?= References: <20250308225902.1208237-1-richard.henderson@linaro.org> <20250308225902.1208237-6-richard.henderson@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/2/25 03:17, Philippe Mathieu-Daudé wrote: > Hi Richard, > > On 8/3/25 23:58, Richard Henderson wrote: >> Some of these bits are actually common to all cpus; while the >> reset have common reservations for target-specific usage. >> While generic code cannot know what the target-specific usage is, >> common code can know what to do with the bits, e.g. single-step. >> >> Tested-by: Philippe Mathieu-Daudé >> Reviewed-by: Philippe Mathieu-Daudé >> Reviewed-by: Pierrick Bouvier >> Signed-off-by: Richard Henderson >> --- >>   include/exec/cpu-all.h       | 53 +-------------------------- >>   include/exec/cpu-interrupt.h | 70 ++++++++++++++++++++++++++++++++++++ >>   include/exec/poison.h        | 13 ------- >>   3 files changed, 71 insertions(+), 65 deletions(-) >>   create mode 100644 include/exec/cpu-interrupt.h > > >> diff --git a/include/exec/poison.h b/include/exec/poison.h >> index 35721366d7..8ed04b3108 100644 >> --- a/include/exec/poison.h >> +++ b/include/exec/poison.h >> @@ -46,19 +46,6 @@ >>   #pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS >> -#pragma GCC poison CPU_INTERRUPT_HARD >> -#pragma GCC poison CPU_INTERRUPT_EXITTB >> -#pragma GCC poison CPU_INTERRUPT_HALT >> -#pragma GCC poison CPU_INTERRUPT_DEBUG >> -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0 >> -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1 >> -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_2 >> -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_3 >> -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_4 >> -#pragma GCC poison CPU_INTERRUPT_TGT_INT_0 >> -#pragma GCC poison CPU_INTERRUPT_TGT_INT_1 >> -#pragma GCC poison CPU_INTERRUPT_TGT_INT_2 > > If I understood correctly yesterday's discussion, these > definitions are internal to target/ and shouldn't be used > by hw/ at all. If this is right, then we need to keep them > poisoned for hw/ code. No. They are used by generic code to mask CPU_INTERRUPT_TGT_EXT_* during single-stepping. We don't know what they mean, but they're all external interrupts. r~