From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org
Subject: Re: [PATCH v4 14/16] target/riscv: Align gprs and fprs in cpu_dump
Date: Tue, 19 Oct 2021 10:42:04 +0800 [thread overview]
Message-ID: <6b5039d8-9d9d-da99-1c56-971b6c484fb7@c-sky.com> (raw)
In-Reply-To: <20211019000108.3678724-15-richard.henderson@linaro.org>
On 2021/10/19 上午8:01, Richard Henderson wrote:
> Allocate 8 columns per register name.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Zhiwei
> ---
> target/riscv/cpu.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4e1920d5f0..f352c2b74c 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -240,7 +240,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env));
> }
> #endif
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
> + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", "pc", env->pc);
> #ifndef CONFIG_USER_ONLY
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
> @@ -290,15 +290,16 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> #endif
>
> for (i = 0; i < 32; i++) {
> - qemu_fprintf(f, " %s " TARGET_FMT_lx,
> + qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
> riscv_int_regnames[i], env->gpr[i]);
> if ((i & 3) == 3) {
> qemu_fprintf(f, "\n");
> }
> }
> +
> if (flags & CPU_DUMP_FPU) {
> for (i = 0; i < 32; i++) {
> - qemu_fprintf(f, " %s %016" PRIx64,
> + qemu_fprintf(f, " %-8s %016" PRIx64,
> riscv_fpr_regnames[i], env->fpr[i]);
> if ((i & 3) == 3) {
> qemu_fprintf(f, "\n");
next prev parent reply other threads:[~2021-10-19 2:43 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 0:00 [PATCH v4 00/16] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-19 0:00 ` [PATCH v4 01/16] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-19 0:00 ` [PATCH v4 02/16] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-19 0:00 ` [PATCH v4 03/16] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-19 0:00 ` [PATCH v4 04/16] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-19 0:00 ` [PATCH v4 05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-19 0:00 ` [PATCH v4 06/16] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-19 0:00 ` [PATCH v4 07/16] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-19 0:01 ` [PATCH v4 08/16] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-19 0:01 ` [PATCH v4 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-19 2:24 ` LIU Zhiwei
2021-10-19 2:30 ` Richard Henderson
2021-10-19 0:01 ` [PATCH v4 10/16] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-19 0:01 ` [PATCH v4 11/16] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-19 0:01 ` [PATCH v4 12/16] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-19 0:01 ` [PATCH v4 13/16] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
2021-10-19 0:01 ` [PATCH v4 14/16] target/riscv: Align gprs and fprs in cpu_dump Richard Henderson
2021-10-19 2:42 ` LIU Zhiwei [this message]
2021-10-19 0:01 ` [PATCH v4 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump Richard Henderson
2021-10-19 2:55 ` Richard Henderson
2021-10-19 0:01 ` [PATCH v4 16/16] target/riscv: Compute mstatus.sd on demand Richard Henderson
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