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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9a3b83sm17192486f8f.33.2025.03.26.07.18.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Mar 2025 07:18:08 -0700 (PDT) Message-ID: <6b943f66-6a2d-4db7-9524-c4c1fa2fbaec@redhat.com> Date: Wed, 26 Mar 2025 15:18:07 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 15/20] hw/arm/smmuv3: Forward invalidation commands to hw Content-Language: en-US To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, linuxarm@huawei.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> <20250311141045.66620-16-shameerali.kolothum.thodi@huawei.com> From: Eric Auger In-Reply-To: <20250311141045.66620-16-shameerali.kolothum.thodi@huawei.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/11/25 3:10 PM, Shameer Kolothum wrote: > From: Nicolin Chen > > Use the provided smmuv3-accel helper functions to issue the > command to physical SMMUv3. > > Signed-off-by: Nicolin Chen > Signed-off-by: Shameer Kolothum > --- > hw/arm/smmuv3-internal.h | 11 ++++++++ > hw/arm/smmuv3.c | 58 +++++++++++++++++++++++++++++++++++++++- > 2 files changed, 68 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index 4602ae6728..546f8faac0 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -235,6 +235,17 @@ static inline bool smmuv3_gerror_irq_enabled(SMMUv3State *s) > #define Q_CONS_WRAP(q) (((q)->cons & WRAP_MASK(q)) >> (q)->log2size) > #define Q_PROD_WRAP(q) (((q)->prod & WRAP_MASK(q)) >> (q)->log2size) > > +static inline int smmuv3_q_ncmds(SMMUQueue *q) > +{ > + uint32_t prod = Q_PROD(q); > + uint32_t cons = Q_CONS(q); > + > + if (Q_PROD_WRAP(q) == Q_CONS_WRAP(q)) > + return prod - cons; > + else > + return WRAP_MASK(q) - cons + prod; > +} > + > static inline bool smmuv3_q_full(SMMUQueue *q) > { > return ((q->cons ^ q->prod) & WRAP_INDEX_MASK(q)) == WRAP_MASK(q); > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 83159db1d4..e0f225d0df 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -1297,10 +1297,18 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) > SMMUCmdError cmd_error = SMMU_CERROR_NONE; > SMMUQueue *q = &s->cmdq; > SMMUCommandType type = 0; > + SMMUCommandBatch batch = {}; > + uint32_t ncmds = 0; > + > > if (!smmuv3_cmdq_enabled(s)) { > return 0; > } > + > + ncmds = smmuv3_q_ncmds(q); > + batch.cmds = g_new0(Cmd, ncmds); > + batch.cons = g_new0(uint32_t, ncmds); > + > /* > * some commands depend on register values, typically CR0. In case those > * register values change while handling the command, spec says it > @@ -1395,6 +1403,13 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) > > trace_smmuv3_cmdq_cfgi_cd(sid); > smmuv3_flush_config(sdev); > + > + if (smmuv3_accel_batch_cmds(sdev->smmu, sdev, &batch, &cmd, > + &q->cons, true)) { > + cmd_error = SMMU_CERROR_ILL; OK so now I see you record the error. You can ignore the previous comment. > + break; > + } > + > break; > } > case SMMU_CMD_TLBI_NH_ASID: > @@ -1418,6 +1433,13 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) > trace_smmuv3_cmdq_tlbi_nh_asid(asid); > smmu_inv_notifiers_all(&s->smmu_state); > smmu_iotlb_inv_asid_vmid(bs, asid, vmid); > + > + if (smmuv3_accel_batch_cmds(bs, NULL, &batch, &cmd, &q->cons, > + false)) { > + cmd_error = SMMU_CERROR_ILL; > + break; > + } > + > break; > } > case SMMU_CMD_TLBI_NH_ALL: > @@ -1445,6 +1467,12 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) > trace_smmuv3_cmdq_tlbi_nsnh(); > smmu_inv_notifiers_all(&s->smmu_state); > smmu_iotlb_inv_all(bs); > + > + if (smmuv3_accel_batch_cmds(bs, NULL, &batch, &cmd, &q->cons, > + false)) { > + cmd_error = SMMU_CERROR_ILL; > + break; > + } > break; > case SMMU_CMD_TLBI_NH_VAA: > case SMMU_CMD_TLBI_NH_VA: > @@ -1453,7 +1481,24 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) > break; > } > smmuv3_range_inval(bs, &cmd, SMMU_STAGE_1); > + > + if (smmuv3_accel_batch_cmds(bs, NULL, &batch, &cmd, &q->cons, > + false)) { > + cmd_error = SMMU_CERROR_ILL; > + break; > + } > + break; > + case SMMU_CMD_ATC_INV: To me the code below shall be put in a separate patch as it introduces the suport for a new cmd. Also it shall be properly documented in the commit msg > + { > + SMMUDevice *sdev = smmu_find_sdev(bs, CMD_SID(&cmd)); > + > + if (smmuv3_accel_batch_cmds(sdev->smmu, sdev, &batch, &cmd, > + &q->cons, true)) { > + cmd_error = SMMU_CERROR_ILL; > + break; > + } > break; > + } > case SMMU_CMD_TLBI_S12_VMALL: > { > int vmid = CMD_VMID(&cmd); > @@ -1485,7 +1530,6 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) > case SMMU_CMD_TLBI_EL2_ASID: > case SMMU_CMD_TLBI_EL2_VA: > case SMMU_CMD_TLBI_EL2_VAA: > - case SMMU_CMD_ATC_INV: > case SMMU_CMD_PRI_RESP: > case SMMU_CMD_RESUME: > case SMMU_CMD_STALL_TERM: > @@ -1511,12 +1555,24 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) > queue_cons_incr(q); > } > > + qemu_mutex_lock(&s->mutex); > + if (!cmd_error && batch.ncmds) { > + if (smmuv3_accel_issue_cmd_batch(bs, &batch)) { > + q->cons = batch.cons[batch.ncmds]; > + cmd_error = SMMU_CERROR_ILL; > + } > + } > + qemu_mutex_unlock(&s->mutex); > + > if (cmd_error) { > trace_smmuv3_cmdq_consume_error(smmu_cmd_string(type), cmd_error); > smmu_write_cmdq_err(s, cmd_error); > smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_CMDQ_ERR_MASK); > } > > + g_free(batch.cmds); > + g_free(batch.cons); > + > trace_smmuv3_cmdq_consume_out(Q_PROD(q), Q_CONS(q), > Q_PROD_WRAP(q), Q_CONS_WRAP(q)); > Eric