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Tue, 5 May 2020 12:26:50 +0000 (GMT) Received: from [9.160.119.241] (unknown [9.160.119.241]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Tue, 5 May 2020 12:26:50 +0000 (GMT) Subject: Re: [PATCH 1/1] target-ppc: fix rlwimi, rlwinm, rlwnm for Clang-9 To: David Gibson References: <20200501190913.25008-1-dbuono@linux.vnet.ibm.com> <20200501190913.25008-2-dbuono@linux.vnet.ibm.com> <20200505050815.GC218517@umbus.fritz.box> From: Daniele Buono Message-ID: <6bce4a90-21c8-0533-e9c2-22fd770da3ee@linux.vnet.ibm.com> Date: Tue, 5 May 2020 08:26:48 -0400 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20200505050815.GC218517@umbus.fritz.box> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-05-05_06:2020-05-04, 2020-05-05 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 malwarescore=0 suspectscore=2 priorityscore=1501 spamscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2005050093 Received-SPF: none client-ip=148.163.158.5; envelope-from=dbuono@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/05 08:27:02 X-ACL-Warn: Detected OS = Linux 3.1-3.10 X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, KHOP_DYNAMIC=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, dbuono@us.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/5/2020 1:08 AM, David Gibson wrote: > On Fri, May 01, 2020 at 03:09:13PM -0400, Daniele Buono wrote: >> Starting with Clang v9, -Wtype-limits is implemented and triggers a >> few "result of comparison is always true" errors when compiling PPC32 >> targets. >> >> The comparisons seem to be necessary only on PPC64, since the >> else branch in PPC32 only has a "g_assert_not_reached();" in all cases. >> >> This patch restructures the code so that PPC32 does not execute the >> check, while PPC64 works like before >> >> Signed-off-by: Daniele Buono > > Urgh. #ifdefs intertangled with if statements gets pretty ugly. But, > then, it's already pretty ugly, so, applied. > Agreed, it's very ugly. After I sent the patch I thought of an alternative that looks like this: bool mask_in_32b = true; #if defined(TARGET_PPC64) if (mask > 0xffffffffu) mask_in_32b = false; #endif if (mask_in_32b) { /* Original if-else untouched using mask_in_32b instead of mask*/ It does have an additional if, but with a bit of luck the compiler may optimize it out (at least for the 32bit case). If you think the final outcome may be better, let me know and I'll send a patch v2 like that. >> --- >> target/ppc/translate.c | 34 +++++++++++++++++++--------------- >> 1 file changed, 19 insertions(+), 15 deletions(-) >> >> diff --git a/target/ppc/translate.c b/target/ppc/translate.c >> index 807d14faaa..9400fa2c7c 100644 >> --- a/target/ppc/translate.c >> +++ b/target/ppc/translate.c >> @@ -1882,6 +1882,7 @@ static void gen_rlwimi(DisasContext *ctx) >> tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); >> } else { >> target_ulong mask; >> + TCGv_i32 t0; >> TCGv t1; >> >> #if defined(TARGET_PPC64) >> @@ -1891,20 +1892,20 @@ static void gen_rlwimi(DisasContext *ctx) >> mask = MASK(mb, me); >> >> t1 = tcg_temp_new(); >> +#if defined(TARGET_PPC64) >> if (mask <= 0xffffffffu) { >> - TCGv_i32 t0 = tcg_temp_new_i32(); >> +#endif >> + t0 = tcg_temp_new_i32(); >> tcg_gen_trunc_tl_i32(t0, t_rs); >> tcg_gen_rotli_i32(t0, t0, sh); >> tcg_gen_extu_i32_tl(t1, t0); >> tcg_temp_free_i32(t0); >> - } else { >> #if defined(TARGET_PPC64) >> + } else { >> tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); >> tcg_gen_rotli_i64(t1, t1, sh); >> -#else >> - g_assert_not_reached(); >> -#endif >> } >> +#endif >> >> tcg_gen_andi_tl(t1, t1, mask); >> tcg_gen_andi_tl(t_ra, t_ra, ~mask); >> @@ -1938,7 +1939,9 @@ static void gen_rlwinm(DisasContext *ctx) >> me += 32; >> #endif >> mask = MASK(mb, me); >> +#if defined(TARGET_PPC64) >> if (mask <= 0xffffffffu) { >> +#endif >> if (sh == 0) { >> tcg_gen_andi_tl(t_ra, t_rs, mask); >> } else { >> @@ -1949,15 +1952,13 @@ static void gen_rlwinm(DisasContext *ctx) >> tcg_gen_extu_i32_tl(t_ra, t0); >> tcg_temp_free_i32(t0); >> } >> - } else { >> #if defined(TARGET_PPC64) >> + } else { >> tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); >> tcg_gen_rotli_i64(t_ra, t_ra, sh); >> tcg_gen_andi_i64(t_ra, t_ra, mask); >> -#else >> - g_assert_not_reached(); >> -#endif >> } >> +#endif >> } >> if (unlikely(Rc(ctx->opcode) != 0)) { >> gen_set_Rc0(ctx, t_ra); >> @@ -1972,6 +1973,9 @@ static void gen_rlwnm(DisasContext *ctx) >> TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; >> uint32_t mb = MB(ctx->opcode); >> uint32_t me = ME(ctx->opcode); >> + TCGv_i32 t0; >> + TCGv_i32 t1; >> + >> target_ulong mask; >> >> #if defined(TARGET_PPC64) >> @@ -1980,9 +1984,11 @@ static void gen_rlwnm(DisasContext *ctx) >> #endif >> mask = MASK(mb, me); >> >> +#if defined(TARGET_PPC64) >> if (mask <= 0xffffffffu) { >> - TCGv_i32 t0 = tcg_temp_new_i32(); >> - TCGv_i32 t1 = tcg_temp_new_i32(); >> +#endif >> + t0 = tcg_temp_new_i32(); >> + t1 = tcg_temp_new_i32(); >> tcg_gen_trunc_tl_i32(t0, t_rb); >> tcg_gen_trunc_tl_i32(t1, t_rs); >> tcg_gen_andi_i32(t0, t0, 0x1f); >> @@ -1990,17 +1996,15 @@ static void gen_rlwnm(DisasContext *ctx) >> tcg_gen_extu_i32_tl(t_ra, t1); >> tcg_temp_free_i32(t0); >> tcg_temp_free_i32(t1); >> - } else { >> #if defined(TARGET_PPC64) >> + } else { >> TCGv_i64 t0 = tcg_temp_new_i64(); >> tcg_gen_andi_i64(t0, t_rb, 0x1f); >> tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); >> tcg_gen_rotl_i64(t_ra, t_ra, t0); >> tcg_temp_free_i64(t0); >> -#else >> - g_assert_not_reached(); >> -#endif >> } >> +#endif >> >> tcg_gen_andi_tl(t_ra, t_ra, mask); >> >