From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH] target/arm: Rearrange cpu64.c so all the CPU initfns are together
Date: Fri, 12 Aug 2022 11:14:24 -0700 [thread overview]
Message-ID: <6bf620cd-6601-e624-ac4b-9d2f5f4a11d0@linaro.org> (raw)
In-Reply-To: <20220812174156.1460714-1-peter.maydell@linaro.org>
On 8/12/22 10:41, Peter Maydell wrote:
> cpu64.c has ended up in a slightly odd order -- it starts with the
> initfns for most of the models-real-hardware CPUs; after that comes a
> bunch of support code for SVE, SME, pauth and LPA2 properties. Then
> come the initfns for the 'host' and 'max' CPU types, and then after
> that one more models-real-hardware CPU initfn, for a64fx. (This
> ordering is partly historical and partly required because a64fx needs
> the SVE properties.)
>
> Reorder the file into:
> * CPU property support functions
> * initfns for real hardware CPUs
> * initfns for host and max
> * class boilerplate
>
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
> I started off thinking this would be a relatively simple "move the
> a64fx initfn up to live with the others", but because we effectively
> have to move all the cpu initfns the diffstat has ended up quite big.
> On the other hand this patch is purely code motion, and the resulting
> order in the file does seem to me to be more sensible.
> ---
> target/arm/cpu64.c | 712 ++++++++++++++++++++++-----------------------
> 1 file changed, 356 insertions(+), 356 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2022-08-12 18:52 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-12 17:41 [PATCH] target/arm: Rearrange cpu64.c so all the CPU initfns are together Peter Maydell
2022-08-12 18:14 ` Richard Henderson [this message]
2022-08-16 0:47 ` Philippe Mathieu-Daudé via
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