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([2602:ae:154e:e201:a7aa:1d1d:c857:5500]) by smtp.gmail.com with ESMTPSA id t17-20020a656091000000b00415d873b7a2sm1625154pgu.11.2022.08.12.11.14.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 12 Aug 2022 11:14:25 -0700 (PDT) Message-ID: <6bf620cd-6601-e624-ac4b-9d2f5f4a11d0@linaro.org> Date: Fri, 12 Aug 2022 11:14:24 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH] target/arm: Rearrange cpu64.c so all the CPU initfns are together Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20220812174156.1460714-1-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20220812174156.1460714-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/12/22 10:41, Peter Maydell wrote: > cpu64.c has ended up in a slightly odd order -- it starts with the > initfns for most of the models-real-hardware CPUs; after that comes a > bunch of support code for SVE, SME, pauth and LPA2 properties. Then > come the initfns for the 'host' and 'max' CPU types, and then after > that one more models-real-hardware CPU initfn, for a64fx. (This > ordering is partly historical and partly required because a64fx needs > the SVE properties.) > > Reorder the file into: > * CPU property support functions > * initfns for real hardware CPUs > * initfns for host and max > * class boilerplate > > Signed-off-by: Peter Maydell > --- > I started off thinking this would be a relatively simple "move the > a64fx initfn up to live with the others", but because we effectively > have to move all the cpu initfns the diffstat has ended up quite big. > On the other hand this patch is purely code motion, and the resulting > order in the file does seem to me to be more sensible. > --- > target/arm/cpu64.c | 712 ++++++++++++++++++++++----------------------- > 1 file changed, 356 insertions(+), 356 deletions(-) Reviewed-by: Richard Henderson r~