qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Richard Henderson <richard.henderson@linaro.org>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com
Subject: Re: [PATCH v2 12/14] target/riscv: Split out the vill from vtype
Date: Wed, 10 Nov 2021 22:26:54 +0800	[thread overview]
Message-ID: <6c0631e7-bb7c-f69c-c5fd-4023c392a7e6@c-sky.com> (raw)
In-Reply-To: <df7ad986-8430-9994-83ac-33db2ec1f2e3@linaro.org>


On 2021/11/10 下午7:23, Richard Henderson wrote:
> On 11/10/21 8:04 AM, LIU Zhiwei wrote:
>> We need not specially process vtype when XLEN changes.
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>>   target/riscv/cpu.h           |  1 +
>>   target/riscv/csr.c           | 15 ++++++++++++++-
>>   target/riscv/machine.c       |  1 +
>>   target/riscv/vector_helper.c |  7 ++-----
>>   4 files changed, 18 insertions(+), 6 deletions(-)
>
> This patch should come before patch 6, which is over-complicated.

Agree.

One question here. Even come before patch 6, we don't have a simple way 
to choose vill and reserved fields from s2 register in patch 6.

>
>> +    target_ulong vill;
>
> This could be bool, though there's no good place to slot it that does 
> not result in unused padding.

As env->vill will be used in read_vtype,  we still need to covert 
env->vill type to target_ulong there.
Is there any benefit to use bool instead of target_ulong?

> Comments should be added to show that this bit is now missing from vtype.
>
>> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
>> index 19e982d3f0..cc4dda4b93 100644
>> --- a/target/riscv/machine.c
>> +++ b/target/riscv/machine.c
>> @@ -104,6 +104,7 @@ static const VMStateDescription vmstate_vector = {
>>               VMSTATE_UINTTL(env.vl, RISCVCPU),
>>               VMSTATE_UINTTL(env.vstart, RISCVCPU),
>>               VMSTATE_UINTTL(env.vtype, RISCVCPU),
>> +            VMSTATE_UINTTL(env.vill, RISCVCPU),
>>               VMSTATE_END_OF_LIST()
>
> This will need a bump to version.
>
>> @@ -45,11 +45,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, 
>> target_ulong s1,
>>       }
>>       if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved 
>> != 0)) {
>>           /* only set vill bit. */
>> -        if (xlen < TARGET_LONG_BITS) {
>> -            env->vtype = FIELD_DP64(0, VTYPE, VILL_XLEN32, 1);
>> -        } else {
>> -            env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
>> -        }
>> +        env->vill = 1;
>> +        env->vtype = 0;
>
> This is fine.
>
> You're missing the updates to cpu_get_tb_cpu_state.

Yes.

Thanks,
Zhiwei

>
>
> r~


  reply	other threads:[~2021-11-10 14:28 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-10  7:04 [PATCH v2 00/14] Support UXL filed in xstatus LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 01/14] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-10 10:18   ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 02/14] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 03/14] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 04/14] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-10  9:42   ` LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 05/14] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-10 10:52   ` Richard Henderson
2021-11-10 13:44     ` LIU Zhiwei
2021-11-10 14:40       ` Richard Henderson
2021-11-11  5:04         ` LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 06/14] target/riscv: Adjust vsetvl " LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-10 10:55   ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 08/14] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 09/14] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-10 11:31   ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 10/14] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-10 11:11   ` Richard Henderson
2021-11-10 14:08     ` LIU Zhiwei
2021-11-10 14:43       ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-10 11:29   ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 12/14] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-10 11:23   ` Richard Henderson
2021-11-10 14:26     ` LIU Zhiwei [this message]
2021-11-10 15:01       ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 13/14] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-10 11:25   ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 14/14] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-10 11:27   ` Richard Henderson
2021-11-10 14:38     ` LIU Zhiwei
2021-11-10 15:02       ` Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=6c0631e7-bb7c-f69c-c5fd-4023c392a7e6@c-sky.com \
    --to=zhiwei_liu@c-sky.com \
    --cc=Alistair.Francis@wdc.com \
    --cc=bin.meng@windriver.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).