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From: Richard Henderson <rth@twiddle.net>
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Date: Wed, 22 Jun 2016 10:12:07 -0700
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Subject: Re: [Qemu-devel] [PATCH v2] Improve the alignment check
 infrastructure
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To: Sergey Sorokin <afarallax@yandex.ru>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>, Peter Crosthwaite <crosthwaite.peter@gmail.com>, Alexander Graf <agraf@suse.de>, "qemu-arm@nongnu.org" <qemu-arm@nongnu.org>, Claudio Fontana <claudio.fontana@huawei.com>, Vassili Karpov <av1474@comtv.ru>

On 06/22/2016 09:30 AM, Sergey Sorokin wrote:
>>      diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
>>      index da10052..3dc38fa 100644
>>      --- a/tcg/ppc/tcg-target.inc.c
>>      +++ b/tcg/ppc/tcg-target.inc.c
>>      @@ -1399,6 +1399,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s,
>>     TCGMemOp opc,
>>           int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
>>           TCGReg base = TCG_AREG0;
>>           TCGMemOp s_bits = opc & MO_SIZE;
>>      + int a_bits = get_alignment_bits(opc);
>>
>>           /* Extract the page index, shifted into place for tlb index. */
>>           if (TCG_TARGET_REG_BITS == 64) {
>>      @@ -1456,14 +1457,21 @@ static TCGReg tcg_out_tlb_read(TCGContext *s,
>>     TCGMemOp opc,
>>                * the bottom bits and thus trigger a comparison failure on
>>                * unaligned accesses
>>                */
>>      + if (a_bits > 0) {
>>      + tcg_debug_assert((((1 << a_bits) - 1) & TLB_FLAGS_MASK) == 0);
>>      + } else {
>>      + a_bits = s_bits;
>>      + }
>>               tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
>>      + (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
>>
>>
>> ppc32 can certainly support over-alignment, just like every other target. It's
>> just that there are some 32-bit parts that don't support unaligned accesses.
>>
>  
> I don't understand your point here.

ppc32 can support a_bits > s_bits.


r~