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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id n14sm2359350pgd.78.2020.06.18.16.51.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 18 Jun 2020 16:51:37 -0700 (PDT) Subject: Re: [PATCH 0/6] Add several Power ISA 3.1 32/64-bit vector instructions To: Lijun Pan , qemu-ppc@nongnu.org, qemu-devel@nongnu.org References: <20200613042029.22321-1-ljp@linux.ibm.com> From: Richard Henderson Message-ID: <6c2f6b83-2132-7042-7df6-3267c9112df0@linaro.org> Date: Thu, 18 Jun 2020 16:51:35 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200613042029.22321-1-ljp@linux.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/12/20 9:20 PM, Lijun Pan wrote: > This patch series add several newly introduced 32/64-bit vector > instructions in Power ISA 3.1. The newly added instructions are > flagged as ISA300 temporarily in vmx-ops.inc.c and vmx-impl.inc.c > to make them compile and function since Power ISA 3.1, together > with next generation processor, has not been fully enabled in QEMU > yet. When Power ISA 3.1 and next generation processor are fully > supported, the flags should be changed. This is not the correct procedure. Step 1 is to add a new define for ISA301, which is not enabled for any processor. Step 2 is to add all of the new instructions, using ISA301. In this way there is no intermediate point in which a 3.01 instruction is enabled for 3.00. In addition, we do not have extra churn simply to change the ISA. Step 3 is to add a new processor for which ISA301 is set. It is often reasonable to have a fake processor named "max" that contains all of the available features. For ppc, I see that "max" is currently aliased to "7400_v2.9". r~