From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>,
Helge Deller <deller@gmx.de>,
Gabriel Brookman <brookmangabriel@gmail.com>
Subject: Re: [PATCH] target/hppa: Set FPCR exception flag bits for non-trapped exceptions
Date: Wed, 22 Oct 2025 21:00:37 +0200 [thread overview]
Message-ID: <6c4d97fc-56fc-417c-9f2b-6a89c9c86591@linaro.org> (raw)
In-Reply-To: <20251017085350.895681-1-peter.maydell@linaro.org>
Cc'ing Gabriel
On 17/10/25 10:53, Peter Maydell wrote:
> In commit ebd394948de4e8 ("target/hppa: Fix FPE exceptions") when
> we added the code for setting up the registers correctly on trapping
> FP exceptions, we accidentally broke the handling of the flag bits
> for non-trapping exceptions.
>
> In update_fr0_op() we incorrectly zero out the flag bits and the C
> bit, so any fp operation would clear previously set flag bits. We
> also stopped setting the flag bits when the fp operation raises
> an exception and the trap is not enabled.
>
> Adjust the code so that we set the Flag bits for every exception that
> happened and where the trap is not enabled. (This is the correct
> behaviour for the case where an instruction triggers two exceptions,
> one of which traps and one of which does not; that can only happen
> for inexact + underflow or inexact + overflow.)
>
> Cc: qemu-stable@nongnu.org
> Fixes: ebd394948de4e8 ("target/hppa: Fix FPE exceptions")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3158
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/hppa/fpu_helper.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
> index 45353202fae..2d272730f60 100644
> --- a/target/hppa/fpu_helper.c
> +++ b/target/hppa/fpu_helper.c
> @@ -94,7 +94,8 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra)
> {
> uint32_t soft_exp = get_float_exception_flags(&env->fp_status);
> uint32_t hard_exp = 0;
> - uint32_t shadow = env->fr0_shadow & 0x3ffffff;
> + uint32_t shadow = env->fr0_shadow;
> + uint32_t to_flag = 0;
> uint32_t fr1 = 0;
>
> if (likely(soft_exp == 0)) {
> @@ -122,6 +123,10 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra)
> fr1 |= hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT);
> }
> }
> + /* Set the Flag bits for every exception that was not enabled */
> + to_flag = hard_exp & ~shadow;
> + shadow |= to_flag << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT);
> +
> env->fr0_shadow = shadow;
> env->fr[0] = (uint64_t)shadow << 32 | fr1;
>
next prev parent reply other threads:[~2025-10-22 19:00 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-17 8:53 [PATCH] target/hppa: Set FPCR exception flag bits for non-trapped exceptions Peter Maydell
2025-10-22 19:00 ` Philippe Mathieu-Daudé [this message]
2025-10-25 15:24 ` Helge Deller
2025-10-28 7:30 ` Philippe Mathieu-Daudé
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