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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-475c428dafesm55172395e9.6.2025.10.22.12.00.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Oct 2025 12:00:38 -0700 (PDT) Message-ID: <6c4d97fc-56fc-417c-9f2b-6a89c9c86591@linaro.org> Date: Wed, 22 Oct 2025 21:00:37 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/hppa: Set FPCR exception flag bits for non-trapped exceptions Content-Language: en-US To: Peter Maydell , qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller , Gabriel Brookman References: <20251017085350.895681-1-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20251017085350.895681-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Cc'ing Gabriel On 17/10/25 10:53, Peter Maydell wrote: > In commit ebd394948de4e8 ("target/hppa: Fix FPE exceptions") when > we added the code for setting up the registers correctly on trapping > FP exceptions, we accidentally broke the handling of the flag bits > for non-trapping exceptions. > > In update_fr0_op() we incorrectly zero out the flag bits and the C > bit, so any fp operation would clear previously set flag bits. We > also stopped setting the flag bits when the fp operation raises > an exception and the trap is not enabled. > > Adjust the code so that we set the Flag bits for every exception that > happened and where the trap is not enabled. (This is the correct > behaviour for the case where an instruction triggers two exceptions, > one of which traps and one of which does not; that can only happen > for inexact + underflow or inexact + overflow.) > > Cc: qemu-stable@nongnu.org > Fixes: ebd394948de4e8 ("target/hppa: Fix FPE exceptions") > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3158 > Signed-off-by: Peter Maydell > --- > target/hppa/fpu_helper.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c > index 45353202fae..2d272730f60 100644 > --- a/target/hppa/fpu_helper.c > +++ b/target/hppa/fpu_helper.c > @@ -94,7 +94,8 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra) > { > uint32_t soft_exp = get_float_exception_flags(&env->fp_status); > uint32_t hard_exp = 0; > - uint32_t shadow = env->fr0_shadow & 0x3ffffff; > + uint32_t shadow = env->fr0_shadow; > + uint32_t to_flag = 0; > uint32_t fr1 = 0; > > if (likely(soft_exp == 0)) { > @@ -122,6 +123,10 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra) > fr1 |= hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT); > } > } > + /* Set the Flag bits for every exception that was not enabled */ > + to_flag = hard_exp & ~shadow; > + shadow |= to_flag << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT); > + > env->fr0_shadow = shadow; > env->fr[0] = (uint64_t)shadow << 32 | fr1; >