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[120.151.179.201]) by smtp.gmail.com with ESMTPSA id rj1sm5208365pjb.49.2022.01.29.01.28.24 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 29 Jan 2022 01:28:25 -0800 (PST) Message-ID: <6c518961-07fc-94d3-1acb-fc4aa99e0d04@linaro.org> Date: Sat, 29 Jan 2022 20:28:21 +1100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH 00/20] tcg: vector improvements Content-Language: en-US From: Richard Henderson To: qemu-devel@nongnu.org References: <20211218194250.247633-1-richard.henderson@linaro.org> In-Reply-To: <20211218194250.247633-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::531 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Ping? Patch 1 is now upstream, but only patches 2-4 have reviews. It applies cleanly to master... r~ On 12/19/21 06:42, Richard Henderson wrote: > Add some opcodes for compound logic operations that were so > far marked as TODO. Implement those for PPC and S390X. > > We do not want to implement 512-bit width operations, because > those trigger a cluster clock slowdown on the current set of > Intel cpus. But there are new operations in avx512 that apply > to 128 and 256-bit vectors, which do not trigger the slowdown, > and those are very interesting. > > > r~ > > > Richard Henderson (20): > tcg/optimize: Fix folding of vector ops > tcg: Add opcodes for vector nand, nor, eqv > tcg/ppc: Implement vector NAND, NOR, EQV > tcg/s390x: Implement vector NAND, NOR, EQV > tcg/i386: Detect AVX512 > tcg/i386: Add tcg_out_evex_opc > tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv > tcg/i386: Implement avx512 variable shifts > tcg/i386: Implement avx512 scalar shift > tcg/i386: Implement avx512 immediate sari shift > tcg/i386: Implement avx512 immediate rotate > tcg/i386: Implement avx512 variable rotate > tcg/i386: Support avx512vbmi2 vector shift-double instructions > tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double > tcg/i386: Remove rotls_vec from tcg_target_op_def > tcg/i386: Expand scalar rotate with avx512 insns > tcg/i386: Implement avx512 min/max/abs > tcg/i386: Implement avx512 multiply > tcg/i386: Implement more logical operations for avx512 > tcg/i386: Implement bitsel for avx512 > > include/qemu/cpuid.h | 20 +- > include/tcg/tcg-opc.h | 3 + > include/tcg/tcg.h | 3 + > tcg/aarch64/tcg-target.h | 3 + > tcg/arm/tcg-target.h | 3 + > tcg/i386/tcg-target-con-set.h | 1 + > tcg/i386/tcg-target.h | 17 +- > tcg/i386/tcg-target.opc.h | 3 + > tcg/ppc/tcg-target.h | 3 + > tcg/s390x/tcg-target.h | 3 + > tcg/optimize.c | 61 ++++-- > tcg/tcg-op-vec.c | 27 ++- > tcg/tcg.c | 6 + > tcg/i386/tcg-target.c.inc | 386 ++++++++++++++++++++++++++++------ > tcg/ppc/tcg-target.c.inc | 15 ++ > tcg/s390x/tcg-target.c.inc | 17 ++ > 16 files changed, 472 insertions(+), 99 deletions(-) >