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[83.42.61.62]) by smtp.gmail.com with ESMTPSA id r12sm12151260wrt.95.2019.07.12.10.10.08 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Fri, 12 Jul 2019 10:10:09 -0700 (PDT) To: "Michael S. Tsirkin" , qemu-devel@nongnu.org References: <20190711192512.31936-1-mst@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: <6c600af7-6590-cdc0-20f3-677b37393693@redhat.com> Date: Fri, 12 Jul 2019 19:10:08 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20190711192512.31936-1-mst@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.66 Subject: Re: [Qemu-devel] [PATCH] xio3130_downstream: typo fix X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/11/19 9:25 PM, Michael S. Tsirkin wrote: > slt ctl/status are passed in incorrect order. > Fix this up. > Fixes: Coverity (CID 1403007) > Signed-off-by: Michael S. Tsirkin > Reported-by: Peter Maydell > --- > hw/pci-bridge/xio3130_downstream.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c > index 899b0fd6c9..182e164f74 100644 > --- a/hw/pci-bridge/xio3130_downstream.c > +++ b/hw/pci-bridge/xio3130_downstream.c > @@ -43,7 +43,7 @@ static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address, > { > uint16_t slt_ctl, slt_sta; > > - pcie_cap_slot_get(d, &slt_sta, &slt_ctl); > + pcie_cap_slot_get(d, &slt_ctl, &slt_sta); > pci_bridge_write_config(d, address, val, len); > pcie_cap_flr_write_config(d, address, val, len); > pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len); >