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References: <20171003062310.9919-1-sandipan@linux.vnet.ibm.com>
From: Richard Henderson <richard.henderson@linaro.org>
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Date: Thu, 5 Oct 2017 08:42:56 -0400
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Subject: Re: [Qemu-devel] [PATCH v3] target/ppc: Fix carry flag setting for
 shift algebraic instructions
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To: Sandipan Das <sandipan@linux.vnet.ibm.com>, david@gibson.dropbear.id.au, agraf@suse.de
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com

On 10/03/2017 02:23 AM, Sandipan Das wrote:
> @@ -231,6 +231,10 @@ target_ulong helper_sraw(CPUPPCState *env, target_ulong value,
>          ret = (int32_t)value >> 31;
>          env->ca = (ret != 0);
>      }
> +
> +    /* update CA32 for ISA v3.0 */
> +    env->ca32 = env->ca;

As I said before, modify ca32 only when ca is modified.
E.g.

  env->ca32 = env->ca = (ret != 0);

> @@ -257,6 +261,10 @@ target_ulong helper_srad(CPUPPCState *env, target_ulong value,
>          ret = (int64_t)value >> 63;
>          env->ca = (ret != 0);
>      }
> +
> +    /* update CA32 for ISA v3.0 */
> +    env->ca32 = env->ca;

Likewise.

> @@ -2192,6 +2192,10 @@ static void gen_srawi(DisasContext *ctx)
>          tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
>          tcg_gen_sari_tl(dst, dst, sh);
>      }
> +
> +    /* update CA32 for ISA v3.0 */
> +    tcg_gen_mov_tl(cpu_ca32, cpu_ca);

Likewise.

> @@ -2269,6 +2273,10 @@ static inline void gen_sradi(DisasContext *ctx, int n)
>          tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
>          tcg_gen_sari_tl(dst, src, sh);
>      }
> +
> +    /* update CA32 for ISA v3.0 */
> +    tcg_gen_mov_tl(cpu_ca32, cpu_ca);

Likewise.


r~