From: Richard Henderson <richard.henderson@linaro.org>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
philmd@linaro.org
Subject: Re: [PATCH v11 4/7] target/riscv: remove 'over' brconds from vector trans
Date: Mon, 11 Mar 2024 07:15:03 -1000 [thread overview]
Message-ID: <6ced24cd-657e-48d2-b273-1e5fc471415e@linaro.org> (raw)
In-Reply-To: <20240311135855.225578-5-dbarboza@ventanamicro.com>
On 3/11/24 03:58, Daniel Henrique Barboza wrote:
> Most of the vector translations has this following pattern at the start:
>
> TCGLabel *over = gen_new_label();
> tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> And then right at the end:
>
> gen_set_label(over);
> return true;
>
> This means that if vstart >= vl we'll not set vstart = 0 at the end of
> the insns - this is done inside the helper that is being skipped. The
> reason why this pattern hasn't been a bigger problem is because the
> conditional vstart >= vl is very rare.
>
> Checking all the helpers in vector_helper.c we see all of them with a
> pattern like this:
>
> for (i = env->vstart; i < vl; i++) {
> (...)
> }
> env->vstart = 0;
>
> Thus they can handle vstart >= vl case gracefully, with the benefit of
> setting env->vstart = 0 during the process.
You'll want to update this comment for VSTART_CHECK_EARLY_EXIT
r~
next prev parent reply other threads:[~2024-03-11 17:16 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-11 13:58 [PATCH v11 0/7] riscv: set vstart_eq_zero on vector insns Daniel Henrique Barboza
2024-03-11 13:58 ` [PATCH v11 1/7] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX() Daniel Henrique Barboza
2024-03-11 13:58 ` [PATCH v11 2/7] trans_rvv.c.inc: set vstart = 0 in int scalar move insns Daniel Henrique Barboza
2024-03-11 13:58 ` [PATCH v11 3/7] target/riscv/vector_helpers: do early exit when vstart >= vl Daniel Henrique Barboza
2024-03-11 17:13 ` Richard Henderson
2024-03-11 13:58 ` [PATCH v11 4/7] target/riscv: remove 'over' brconds from vector trans Daniel Henrique Barboza
2024-03-11 17:15 ` Richard Henderson [this message]
2024-03-11 13:58 ` [PATCH v11 5/7] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls Daniel Henrique Barboza
2024-03-11 13:58 ` [PATCH v11 6/7] target/riscv: enable 'vstart_eq_zero' in the end of insns Daniel Henrique Barboza
2024-03-11 13:58 ` [PATCH v11 7/7] target/riscv/vector_helper.c: optimize loops in ldst helpers Daniel Henrique Barboza
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