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From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: "Anton Johansson" <anjo@rev.ng>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org,
	alistair.francis@wdc.com, palmer@dabbelt.com
Subject: Re: [PATCH v2 03/33] target/riscv: Fix size of mhartid
Date: Thu, 2 Oct 2025 11:34:13 -0700	[thread overview]
Message-ID: <6d0f87e5-a46a-4596-9b04-97b88203358b@linaro.org> (raw)
In-Reply-To: <o4orrvxjkhwz3r2q4dotnkpffwm2deamlgvffnxk26z622yfgo@fksfmpmm35ef>

On 10/1/25 1:28 AM, Anton Johansson wrote:
> On 01/10/25, Philippe Mathieu-Daudé wrote:
>> On 1/10/25 09:32, Anton Johansson wrote:
>>> and update formatting in log.
>>>
>>> Signed-off-by: Anton Johansson <anjo@rev.ng>
>>> ---
>>>    target/riscv/cpu.h         | 2 +-
>>>    target/riscv/cpu_helper.c  | 2 +-
>>>    target/riscv/machine.c     | 2 +-
>>>    target/riscv/tcg/tcg-cpu.c | 2 +-
>>>    4 files changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>>> index 736e4f6daa..3235108112 100644
>>> --- a/target/riscv/cpu.h
>>> +++ b/target/riscv/cpu.h
>>> @@ -279,7 +279,7 @@ struct CPUArchState {
>>>        target_ulong geilen;
>>>        uint64_t resetvec;
>>> -    target_ulong mhartid;
>>> +    uint64_t mhartid;
>>>        /*
>>>         * For RV32 this is 32-bit mstatus and 32-bit mstatush.
>>>         * For RV64 this is a 64-bit mstatus.
>>
>>
>>> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
>>> index 99e46c3136..328fb674e1 100644
>>> --- a/target/riscv/machine.c
>>> +++ b/target/riscv/machine.c
>>> @@ -425,7 +425,7 @@ const VMStateDescription vmstate_riscv_cpu = {
>>>            VMSTATE_UINTTL(env.priv, RISCVCPU),
>>>            VMSTATE_BOOL(env.virt_enabled, RISCVCPU),
>>>            VMSTATE_UINT64(env.resetvec, RISCVCPU),
>>> -        VMSTATE_UINTTL(env.mhartid, RISCVCPU),
>>> +        VMSTATE_UINT64(env.mhartid, RISCVCPU),
>>
>> The problem is you break the migration stream again. Maybe simpler to
>> just squash with previous patch?
>>
>> Thay said, IIUC mhartid is only set once in riscv_hart_realize().
>> I suspect it is pointless to migrate it.
> 
> Right, wrt the other vmstate changes I only bumped the version on first
> modification.  Maybe it makes more sense to group changes based on what
> vmstate they touch?  If excessive version bumping is a problem that is.

As long as it's bumped once in the series, I think it's acceptable.
No one will try to bisect that for migration.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>



  reply	other threads:[~2025-10-02 18:35 UTC|newest]

Thread overview: 99+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-01  7:32 [PATCH v2 00/33] single-binary: Make riscv cpu.h target independent Anton Johansson via
2025-10-01  7:32 ` [PATCH v2 01/33] target/riscv: Use 32 bits for misa extensions Anton Johansson via
2025-10-01  7:34   ` Philippe Mathieu-Daudé
2025-10-02  1:56   ` Alistair Francis
2025-10-02 18:31   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 02/33] target/riscv: Fix size of trivial CPUArchState fields Anton Johansson via
2025-10-02  1:57   ` Alistair Francis
2025-10-02 18:31   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 03/33] target/riscv: Fix size of mhartid Anton Johansson via
2025-10-01  7:38   ` Philippe Mathieu-Daudé
2025-10-01  8:28     ` Anton Johansson via
2025-10-02 18:34       ` Pierrick Bouvier [this message]
2025-10-01  7:32 ` [PATCH v2 04/33] target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val() Anton Johansson via
2025-10-02 18:50   ` Pierrick Bouvier
2025-10-02 23:34   ` Alistair Francis
2025-10-07 11:08     ` Anton Johansson via
2025-10-15  2:55       ` Alistair Francis
2025-10-15  9:58         ` Anton Johansson via
2025-10-16  4:01           ` Alistair Francis
2025-10-17 14:24             ` Anton Johansson via
2025-10-23  1:54               ` Alistair Francis
2025-10-01  7:32 ` [PATCH v2 05/33] target/riscv: Combine mhpmevent and mhpmeventh Anton Johansson via
2025-10-01  7:39   ` Philippe Mathieu-Daudé
2025-10-02 19:09     ` Pierrick Bouvier
2025-10-02 23:52       ` Alistair Francis
2025-10-02 19:08   ` Pierrick Bouvier
2025-10-02 19:33     ` Pierrick Bouvier
2025-10-02 23:55       ` Alistair Francis
2025-10-07 11:29         ` Anton Johansson via
2025-10-14 11:25         ` Anton Johansson via
2025-10-01  7:32 ` [PATCH v2 06/33] target/riscv: Combine mcyclecfg and mcyclecfgh Anton Johansson via
2025-10-02 19:13   ` Pierrick Bouvier
2025-10-03  0:05   ` Alistair Francis
2025-10-01  7:32 ` [PATCH v2 07/33] target/riscv: Combine minstretcfg and minstretcfgh Anton Johansson via
2025-10-02 19:14   ` Pierrick Bouvier
2025-10-03  0:06   ` Alistair Francis
2025-10-01  7:32 ` [PATCH v2 08/33] target/riscv: Combine mhpmcounter and mhpmcounterh Anton Johansson via
2025-10-02 19:24   ` Pierrick Bouvier
2025-10-02 19:25   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 09/33] target/riscv: Fix size of gpr and gprh Anton Johansson via
2025-10-01  7:42   ` Philippe Mathieu-Daudé
2025-10-03  9:00     ` Anton Johansson via
2025-10-01  7:32 ` [PATCH v2 10/33] target/riscv: Fix size of vector CSRs Anton Johansson via
2025-10-02 19:42   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 11/33] target/riscv: Fix size of pc, load_[val|res] Anton Johansson via
2025-10-02 19:54   ` Pierrick Bouvier
2025-10-03 12:43     ` Anton Johansson via
2025-10-01  7:32 ` [PATCH v2 12/33] target/riscv: Fix size of frm and fflags Anton Johansson via
2025-10-02 19:57   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 13/33] target/riscv: Fix size of badaddr and bins Anton Johansson via
2025-10-02 20:02   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 14/33] target/riscv: Fix size of guest_phys_fault_addr Anton Johansson via
2025-10-02 20:03   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 15/33] target/riscv: Fix size of priv_ver and vext_ver Anton Johansson via
2025-10-02 20:03   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 16/33] target/riscv: Fix size of retxh Anton Johansson via
2025-10-02 20:05   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 17/33] target/riscv: Fix size of ssp Anton Johansson via
2025-10-02 20:06   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 18/33] target/riscv: Fix size of excp_uw2 Anton Johansson via
2025-10-02 20:06   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 19/33] target/riscv: Fix size of sw_check_code Anton Johansson via
2025-10-02 20:07   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 20/33] target/riscv: Fix size of priv Anton Johansson via
2025-10-02 20:07   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 21/33] target/riscv: Fix size of gei fields Anton Johansson via
2025-10-02 20:08   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 22/33] target/riscv: Fix size of [m|s|vs]iselect fields Anton Johansson via
2025-10-02 20:09   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 23/33] target/riscv: Fix arguments to board IMSIC emulation callbacks Anton Johansson via
2025-10-02 20:15   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 24/33] target/riscv: Fix size of irq_overflow_left Anton Johansson via
2025-10-02 20:15   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 25/33] target/riscv: Indent PMUFixedCtrState correctly Anton Johansson via
2025-10-01  7:43   ` Philippe Mathieu-Daudé
2025-10-02 20:15   ` Pierrick Bouvier
2025-10-01  7:32 ` [PATCH v2 26/33] target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() Anton Johansson via
2025-10-01  7:43   ` Philippe Mathieu-Daudé
2025-10-02 20:15   ` Pierrick Bouvier
2025-10-01  7:33 ` [PATCH v2 27/33] target/riscv: Replace target_ulong in riscv_ctr_add_entry() Anton Johansson via
2025-10-01  7:44   ` Philippe Mathieu-Daudé
2025-10-02 20:19   ` Pierrick Bouvier
2025-10-01  7:33 ` [PATCH v2 28/33] target/riscv: Fix size of trigger data Anton Johansson via
2025-10-01  7:46   ` Philippe Mathieu-Daudé
2025-10-02 20:19   ` Pierrick Bouvier
2025-10-01  7:33 ` [PATCH v2 29/33] target/riscv: Fix size of mseccfg Anton Johansson via
2025-10-01  7:46   ` Philippe Mathieu-Daudé
2025-10-02 20:20   ` Pierrick Bouvier
2025-10-01  7:33 ` [PATCH v2 30/33] target/riscv: Move debug.h include away from cpu.h Anton Johansson via
2025-10-02 20:21   ` Pierrick Bouvier
2025-10-03 12:52     ` Anton Johansson via
2025-10-01  7:33 ` [PATCH v2 31/33] target/riscv: Move CSR declarations to separate csr.h header Anton Johansson via
2025-10-02 20:22   ` Pierrick Bouvier
2025-10-01  7:33 ` [PATCH v2 32/33] target/riscv: Introduce externally facing CSR access functions Anton Johansson via
2025-10-02 20:24   ` Pierrick Bouvier
2025-10-01  7:33 ` [PATCH v2 33/33] target/riscv: Make pmp.h target_ulong agnostic Anton Johansson via
2025-10-01  7:49   ` Philippe Mathieu-Daudé
2025-10-03 12:57     ` Anton Johansson via
2025-10-02 20:23   ` Pierrick Bouvier

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