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Thu, 02 Oct 2025 11:34:14 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-28e8d1d24aesm27627575ad.118.2025.10.02.11.34.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Oct 2025 11:34:14 -0700 (PDT) Message-ID: <6d0f87e5-a46a-4596-9b04-97b88203358b@linaro.org> Date: Thu, 2 Oct 2025 11:34:13 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 03/33] target/riscv: Fix size of mhartid Content-Language: en-US To: Anton Johansson , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com References: <20251001073306.28573-1-anjo@rev.ng> <20251001073306.28573-4-anjo@rev.ng> From: Pierrick Bouvier In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/1/25 1:28 AM, Anton Johansson wrote: > On 01/10/25, Philippe Mathieu-Daudé wrote: >> On 1/10/25 09:32, Anton Johansson wrote: >>> and update formatting in log. >>> >>> Signed-off-by: Anton Johansson >>> --- >>> target/riscv/cpu.h | 2 +- >>> target/riscv/cpu_helper.c | 2 +- >>> target/riscv/machine.c | 2 +- >>> target/riscv/tcg/tcg-cpu.c | 2 +- >>> 4 files changed, 4 insertions(+), 4 deletions(-) >>> >>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >>> index 736e4f6daa..3235108112 100644 >>> --- a/target/riscv/cpu.h >>> +++ b/target/riscv/cpu.h >>> @@ -279,7 +279,7 @@ struct CPUArchState { >>> target_ulong geilen; >>> uint64_t resetvec; >>> - target_ulong mhartid; >>> + uint64_t mhartid; >>> /* >>> * For RV32 this is 32-bit mstatus and 32-bit mstatush. >>> * For RV64 this is a 64-bit mstatus. >> >> >>> diff --git a/target/riscv/machine.c b/target/riscv/machine.c >>> index 99e46c3136..328fb674e1 100644 >>> --- a/target/riscv/machine.c >>> +++ b/target/riscv/machine.c >>> @@ -425,7 +425,7 @@ const VMStateDescription vmstate_riscv_cpu = { >>> VMSTATE_UINTTL(env.priv, RISCVCPU), >>> VMSTATE_BOOL(env.virt_enabled, RISCVCPU), >>> VMSTATE_UINT64(env.resetvec, RISCVCPU), >>> - VMSTATE_UINTTL(env.mhartid, RISCVCPU), >>> + VMSTATE_UINT64(env.mhartid, RISCVCPU), >> >> The problem is you break the migration stream again. Maybe simpler to >> just squash with previous patch? >> >> Thay said, IIUC mhartid is only set once in riscv_hart_realize(). >> I suspect it is pointless to migrate it. > > Right, wrt the other vmstate changes I only bumped the version on first > modification. Maybe it makes more sense to group changes based on what > vmstate they touch? If excessive version bumping is a problem that is. As long as it's bumped once in the series, I think it's acceptable. No one will try to bisect that for migration. Reviewed-by: Pierrick Bouvier