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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id b17sm2260660wrx.15.2019.12.02.22.27.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Dec 2019 22:27:16 -0800 (PST) Subject: Re: [PATCH v4 17/40] target/arm: Tidy ARMMMUIdx m-profile definitions To: Richard Henderson , qemu-devel@nongnu.org References: <20191203022937.1474-1-richard.henderson@linaro.org> <20191203022937.1474-18-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <6d9a0d67-e852-8590-8937-090b67e34c55@redhat.com> Date: Tue, 3 Dec 2019 07:27:15 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191203022937.1474-18-richard.henderson@linaro.org> Content-Language: en-US X-MC-Unique: bUffgAY8Mle2fWwl4jl0Qw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/3/19 3:29 AM, Richard Henderson wrote: > Replace the magic numbers with the relevant ARM_MMU_IDX_M_* constants. > Keep the definitions short by referencing previous symbols. Nice trick :) Reviewed-by: Philippe Mathieu-Daud=E9 >=20 > Signed-off-by: Richard Henderson > --- > target/arm/cpu.h | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) >=20 > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 6ba5126852..015301e93a 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -2871,14 +2871,14 @@ typedef enum ARMMMUIdx { > ARMMMUIdx_SE0 =3D 4 | ARM_MMU_IDX_A, > ARMMMUIdx_SE1 =3D 5 | ARM_MMU_IDX_A, > ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_A, > - ARMMMUIdx_MUser =3D 0 | ARM_MMU_IDX_M, > - ARMMMUIdx_MPriv =3D 1 | ARM_MMU_IDX_M, > - ARMMMUIdx_MUserNegPri =3D 2 | ARM_MMU_IDX_M, > - ARMMMUIdx_MPrivNegPri =3D 3 | ARM_MMU_IDX_M, > - ARMMMUIdx_MSUser =3D 4 | ARM_MMU_IDX_M, > - ARMMMUIdx_MSPriv =3D 5 | ARM_MMU_IDX_M, > - ARMMMUIdx_MSUserNegPri =3D 6 | ARM_MMU_IDX_M, > - ARMMMUIdx_MSPrivNegPri =3D 7 | ARM_MMU_IDX_M, > + ARMMMUIdx_MUser =3D ARM_MMU_IDX_M, > + ARMMMUIdx_MPriv =3D ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, > + ARMMMUIdx_MUserNegPri =3D ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, > + ARMMMUIdx_MPrivNegPri =3D ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, > + ARMMMUIdx_MSUser =3D ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, > + ARMMMUIdx_MSPriv =3D ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, > + ARMMMUIdx_MSUserNegPri =3D ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, > + ARMMMUIdx_MSPrivNegPri =3D ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, > /* Indexes below here don't have TLBs and are used only for AT syst= em > * instructions or for the first stage of an S12 page table walk. > */ >=20