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([2602:47:d483:7301:9e4d:b830:d4fd:9164]) by smtp.gmail.com with ESMTPSA id g5-20020a633745000000b00563da87a52dsm1774337pgn.40.2023.08.10.09.55.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Aug 2023 09:55:17 -0700 (PDT) Message-ID: <6dbafe59-f7ce-12f6-e8c7-eefc7665f598@linaro.org> Date: Thu, 10 Aug 2023 09:55:16 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH 12/24] tcg/aarch64: Implement negsetcond_* Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org References: <20230808031143.50925-1-richard.henderson@linaro.org> <20230808031143.50925-13-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.156, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/10/23 09:39, Peter Maydell wrote: >> + case INDEX_op_negsetcond_i32: >> + a2 = (int32_t)a2; >> + /* FALLTHRU */ > > I see this is what we already do for setcond and movcond, > but how does it work when the 2nd input is a register? > Or is reg-reg guaranteed to always use the _i64 op? For reg-reg, a2 < 31, so the sign-extend does nothing. r~