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([2a01:e0a:280:24f0:9db0:474c:ff43:9f5c]) by smtp.gmail.com with ESMTPSA id m15-20020adffe4f000000b0033e5c54d0d9sm2153343wrs.38.2024.03.22.07.08.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 Mar 2024 07:08:10 -0700 (PDT) Message-ID: <6dfb82c0-d2c0-4618-94b0-2e2561534d96@redhat.com> Date: Fri, 22 Mar 2024 15:08:09 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Subject: Re: [PATCH 0/4] hw/nmi: Remove @cpu_index argument To: Peter Maydell , Mark Burton Cc: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , "qemu-devel@nongnu.org" , Markus Armbruster , "qemu-s390x@nongnu.org" , "qemu-ppc@nongnu.org" , Christian Borntraeger , Manos Pitsidianakis References: <20240220150833.13674-1-philmd@linaro.org> <59C20F1A-FCFE-4E26-B511-A6C0E1EF6F61@qti.qualcomm.com> <23BCD870-16A1-4AF9-9308-2788178F511B@qti.qualcomm.com> Content-Language: en-US, fr In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=clegoate@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.222, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/20/24 16:00, Peter Maydell wrote: > On Wed, 20 Mar 2024 at 14:10, Mark Burton wrote: >> I’d broaden this to all ’signals’ (IRQ, Reset etc) - and I guess >> similar statements apply, with the “bridge” between the function >> and the GPIO mechanism moved closer or further from the originator(s) >> of the activity. >> >> The issue isn’t my “machine” model, rather the compose-ability of >> (any) such machine. A-priori, a model writer doesn’t know if they >> should respond directly to an NMI or not - Hence they dont know if >> they should implement the TYPE_NMI or not. That’s a decision only >> the machine composer knows. >> My suggestion would be to use a GPIO interface to models, which can >> then be appropriately wired. (And, hence, to have a single place >> that implements the TYPE_NMI interface and provides the GPIO wire >> ready for wiring to appropriate devices). > > I feel like that's a long way in the future, but my back-of-the-envelope > design sketch of that is that the TYPE_MACHINE class that's implementing > the "I am just a container for all the devices that the user has > specified and wired together" machine would itself implement TYPE_NMI and > when an NMI came in it would assert a GPIO line that the user could > wire up, or not wire up, as they chose. > > Right now we can't do that though, because, among other reasons, > TYPE_MACHINE isn't a TYPE_DEVICE. (I do want to fix that, though: > I'm hoping it won't be too difficult.) Oh that's interesting. Will that introduce an extra level of container with multiple machines below ? /qemu /machine[0] ... /peripheral (container) /peripheral-anon (container) /machine[1] ... /peripheral (container) /peripheral-anon (container) /unattached (container) ... /sysbus (System) /system[0] (memory-region) Thanks, C.