qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: Re: [PATCH for-6.1 v6 11/17] hw/core: Introduce CPUClass.gdb_adjust_breakpoint
Date: Tue, 20 Jul 2021 11:08:49 -1000	[thread overview]
Message-ID: <6e101005-ce67-3179-b446-c9b963b6bda2@linaro.org> (raw)
In-Reply-To: <CAFEAcA93CkPxmWCnSDaaJ01iTZ2KbabFu_cBKp7O9+BDHHmKfw@mail.gmail.com>

On 7/20/21 10:56 AM, Peter Maydell wrote:
> On Tue, 20 Jul 2021 at 20:54, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> This will allow a breakpoint hack to move out of AVR's translator.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> 
>> diff --git a/cpu.c b/cpu.c
>> index 83059537d7..91d9e38acb 100644
>> --- a/cpu.c
>> +++ b/cpu.c
>> @@ -267,8 +267,13 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
>>   int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
>>                             CPUBreakpoint **breakpoint)
>>   {
>> +    CPUClass *cc = CPU_GET_CLASS(cpu);
>>       CPUBreakpoint *bp;
>>
>> +    if (cc->gdb_adjust_breakpoint) {
>> +        pc = cc->gdb_adjust_breakpoint(cpu, pc);
>> +    }
>> +
>>       bp = g_malloc(sizeof(*bp));
>>
>>       bp->pc = pc;
>> @@ -294,8 +299,13 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
>>   /* Remove a specific breakpoint.  */
>>   int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
>>   {
>> +    CPUClass *cc = CPU_GET_CLASS(cpu);
>>       CPUBreakpoint *bp;
>>
>> +    if (cc->gdb_adjust_breakpoint) {
>> +        pc = cc->gdb_adjust_breakpoint(cpu, pc);
>> +    }
>> +
>>       QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
>>           if (bp->pc == pc && bp->flags == flags) {
>>               cpu_breakpoint_remove_by_ref(cpu, bp);
>> --
> 
> So previously for AVR we would have considered the bp at 0x100
> and the one at 0x800100 as distinct (in the sense that the only way
> the gdb remote protocol distinguishes breakpoints is by "what address",
> and these have different addresses). After this change, they won't
> be distinct, because if you set a bp at 0x100 and 0x800100 and then
> try to remove the one at 0x100 we might remove the 0x800100 one,
> because we're storing only the adjusted-address, not the one gdb used.
> 
> This might not matter in practice...

I don't think it will matter.

Currently, if it sets both 0x100 and 0x800100, then we'll record two breakpoints, and with 
either we'll raise EXCP_DEBUG when pc == 0x100.

Afterward, we'll have two CPUBreakpoint structures that both contain 0x100, and when pc == 
0x100 we'll raise EXCP_DEBUG.  If gdb removes the breakpoint at 0x800100, we'll remove one 
of the two CPUBreakpoint.  But we'll still stop at 0x100, as expected.  When it removes 
the breakpoint at 0x100, both CPUBreakpoint structures will be gone.

In principal, gdb could now add a breakpoint at 0x800100 and remove it with 0x100, where 
it could not before.  But I don't expect that to happen.  If we reported any kind of 
status to gdb re the breakpoint insertion or removal (e.g. bp not found), then it might 
matter, but we don't.

Practically, this is working around what I'd call a gdb bug wrt avr.  Which may even have 
been fixed -- I haven't looked.


r~


  reply	other threads:[~2021-07-20 21:09 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-20 19:54 [PATCH for-6.1 v6 00/17] tcg: breakpoint reorg Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 01/17] accel/tcg: Reduce CF_COUNT_MASK to match TCG_MAX_INSNS Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 02/17] accel/tcg: Move curr_cflags into cpu-exec.c Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 03/17] target/alpha: Drop goto_tb path in gen_call_pal Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 04/17] accel/tcg: Add CF_NO_GOTO_TB and CF_NO_GOTO_PTR Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 05/17] accel/tcg: Drop CF_NO_GOTO_PTR from -d nochain Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 06/17] accel/tcg: Handle -singlestep in curr_cflags Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 07/17] accel/tcg: Use CF_NO_GOTO_{TB, PTR} in cpu_exec_step_atomic Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 08/17] hw/core: Introduce TCGCPUOps.debug_check_breakpoint Richard Henderson
2021-07-21 10:33   ` Alex Bennée
2021-07-20 19:54 ` [PATCH for-6.1 v6 09/17] target/arm: Implement debug_check_breakpoint Richard Henderson
2021-07-21 10:35   ` Alex Bennée
2021-07-20 19:54 ` [PATCH for-6.1 v6 10/17] target/i386: " Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 11/17] hw/core: Introduce CPUClass.gdb_adjust_breakpoint Richard Henderson
2021-07-20 20:56   ` Peter Maydell
2021-07-20 21:08     ` Richard Henderson [this message]
2021-07-20 21:53       ` Philippe Mathieu-Daudé
2021-07-20 22:23         ` Philippe Mathieu-Daudé
2021-07-21  9:56           ` Alex Bennée
2021-07-21  6:12         ` Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 12/17] target/avr: Implement gdb_adjust_breakpoint Richard Henderson
2021-07-20 22:09   ` Philippe Mathieu-Daudé
2021-07-20 19:54 ` [PATCH for-6.1 v6 13/17] accel/tcg: Merge tb_find into its only caller Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 14/17] accel/tcg: Move breakpoint recognition outside translation Richard Henderson
2023-11-28 11:08   ` Philippe Mathieu-Daudé
2023-11-28 18:05     ` Richard Henderson
2023-11-29 15:41       ` Max Filippov
2021-07-20 19:54 ` [PATCH for-6.1 v6 15/17] accel/tcg: Remove TranslatorOps.breakpoint_check Richard Henderson
2021-07-20 20:45   ` Peter Maydell
2021-07-20 22:11   ` Philippe Mathieu-Daudé
2021-07-20 19:54 ` [PATCH for-6.1 v6 16/17] accel/tcg: Hoist tb_cflags to a local in translator_loop Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 17/17] accel/tcg: Record singlestep_enabled in tb->cflags Richard Henderson
2021-07-20 20:47   ` Peter Maydell
2021-07-21 10:38   ` Alex Bennée
2021-07-21 16:41     ` Richard Henderson
2021-07-21 16:48       ` Alex Bennée
2021-07-20 21:47 ` [PATCH for-6.1 v6 00/17] tcg: breakpoint reorg Mark Cave-Ayland

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=6e101005-ce67-3179-b446-c9b963b6bda2@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=alex.bennee@linaro.org \
    --cc=f4bug@amsat.org \
    --cc=mark.cave-ayland@ilande.co.uk \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).