From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair23@gmail.com>,
Frank Chang <frank.chang@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Chih-Min Chao <chihmin.chao@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Kito Cheng <kito.cheng@sifive.com>
Subject: Re: [PATCH v3 3/6] target/riscv: zfh: half-precision convert and move
Date: Sun, 17 Oct 2021 22:53:02 -0700 [thread overview]
Message-ID: <6e208ab3-013e-6109-a93a-8653c03e06de@linaro.org> (raw)
In-Reply-To: <CAKmqyKNb6_b+fS3Ofi1U7wiUwhnwa_0P5G3Go0UFA-ZqSO+yeQ@mail.gmail.com>
On 10/17/21 4:59 PM, Alistair Francis wrote:
>> +#if defined(TARGET_RISCV64)
>> + /* 16 bits -> 64 bits */
>> + tcg_gen_ext16s_tl(dest, cpu_fpr[a->rs1]);
>> +#else
>> + /* 16 bits -> 32 bits */
>> + tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]);
>> + tcg_gen_ext16s_tl(dest, dest);
>> +#endif
> Can we use is_32bit(ctx) instead?
No. This is about sizeof(target_long), not the current cpu state.
It would be possible to use
tcg_gen_trunc_i64_tl
tcg_gen_ext16s_tl
but we have a couple of other instances of the same thing.
r~
next prev parent reply other threads:[~2021-10-18 5:55 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-16 9:07 [PATCH v3 0/6] target/riscv: support Zfh, Zfhmin extension v0.1 frank.chang
2021-10-16 9:07 ` [PATCH v3 1/6] target/riscv: zfh: half-precision load and store frank.chang
2021-10-18 0:03 ` Alistair Francis
2021-10-18 2:15 ` Frank Chang
2021-10-18 4:28 ` Alistair Francis
2021-10-16 9:07 ` [PATCH v3 2/6] target/riscv: zfh: half-precision computational frank.chang
2021-10-17 23:50 ` Alistair Francis
2021-10-16 9:07 ` [PATCH v3 3/6] target/riscv: zfh: half-precision convert and move frank.chang
2021-10-17 23:59 ` Alistair Francis
2021-10-18 5:53 ` Richard Henderson [this message]
2021-10-18 6:11 ` Alistair Francis
2021-10-16 9:07 ` [PATCH v3 4/6] target/riscv: zfh: half-precision floating-point compare frank.chang
2021-10-18 0:00 ` Alistair Francis
2021-10-16 9:07 ` [PATCH v3 5/6] target/riscv: zfh: half-precision floating-point classify frank.chang
2021-10-18 0:01 ` Alistair Francis
2021-10-16 9:07 ` [PATCH v3 6/6] target/riscv: zfh: implement zfhmin extension frank.chang
2021-10-18 0:05 ` Alistair Francis
2021-10-16 18:03 ` [PATCH v3 0/6] target/riscv: support Zfh, Zfhmin extension v0.1 Richard Henderson
2021-10-17 0:23 ` Frank Chang
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