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From: Richard Henderson <richard.henderson@linaro.org>
To: Deepak Gupta <debug@rivosinc.com>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com,
	Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
	liwei1518@gmail.com, dbarboza@ventanamicro.com,
	zhiwei_liu@linux.alibaba.com, pbonzini@redhat.com,
	jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com
Subject: Re: [PATCH v4 13/16] target/riscv: compressed encodings for sspush and sspopchk
Date: Fri, 16 Aug 2024 17:28:29 +1000	[thread overview]
Message-ID: <6e236767-a1a1-41ca-8f7f-10d6247656b9@linaro.org> (raw)
In-Reply-To: <Zr74Axtj/871L5Nj@debug.ba.rivosinc.com>

On 8/16/24 16:56, Deepak Gupta wrote:
>>> +  c_sspush        011 0  00001  00000 01 rs2=1 rs1=0 # c.sspush x1 carving out of zcmops
>>> +  c_sspopchk      011 0  00101  00000 01 rs1=5 rd=0 # c.sspopchk x5 carving out of zcmops
...
>> This indirection is pointless.  Have the decoder invoke the proper insn in the first 
>> place.  Identically with how we're treating 'addi', for instance.
>>
> 
> I was getting compilation error. How to reconcile with arugment sets between
> insn32.decode and insn16.decode. Earlier I was doing that and didn't need it.
> But after removing indirection in arguments and using single use format, type for
> structs instruction arguments ends up conflicting and compiler complains.

Ah, for that you need to use named argument sets.  In this case,

sspush     .... &r2_s rs2=1 rs1=0
sspopchk   .... &r2   rs2=5 rd=0

in both insn32.decode and insn16.decode


r~


  reply	other threads:[~2024-08-16  7:29 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-16  1:06 [PATCH v4 00/16] riscv support for control flow integrity extensions Deepak Gupta
2024-08-16  1:06 ` [PATCH v4 01/16] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-16  1:06 ` [PATCH v4 02/16] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-16  2:56   ` Richard Henderson
2024-08-16  1:06 ` [PATCH v4 03/16] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-16  2:59   ` Richard Henderson
2024-08-16  6:45     ` Deepak Gupta
2024-08-16  1:06 ` [PATCH v4 04/16] target/riscv: additional code information for sw check Deepak Gupta
2024-08-16  1:06 ` [PATCH v4 05/16] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-16  3:41   ` Richard Henderson
2024-08-16  6:49     ` Deepak Gupta
2024-08-16  1:07 ` [PATCH v4 06/16] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-16  3:59   ` Richard Henderson
2024-08-16  1:07 ` [PATCH v4 07/16] disas/riscv: enabled `lpad` disassembly Deepak Gupta
2024-08-16  4:00   ` Richard Henderson
2024-08-16  1:07 ` [PATCH v4 08/16] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-16  1:07 ` [PATCH v4 09/16] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-16  1:07 ` [PATCH v4 10/16] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-16  1:07 ` [PATCH v4 11/16] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-16  5:35   ` Richard Henderson
2024-08-16  1:07 ` [PATCH v4 12/16] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-16  5:43   ` Richard Henderson
2024-08-16  1:07 ` [PATCH v4 13/16] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-16  5:09   ` Richard Henderson
2024-08-16  6:56     ` Deepak Gupta
2024-08-16  7:28       ` Richard Henderson [this message]
2024-08-16  1:07 ` [PATCH v4 14/16] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-16  1:07 ` [PATCH v4 15/16] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-08-16  1:07 ` [PATCH v4 16/16] target/riscv: add trace-hooks for each case of sw-check exception Deepak Gupta
2024-08-16  5:52   ` Richard Henderson
2024-08-16  7:06     ` Deepak Gupta

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