From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH v4 066/163] tcg: Convert ctpop to TCGOutOpUnary
Date: Tue, 15 Apr 2025 14:14:31 -0700 [thread overview]
Message-ID: <6e56a242-c70f-4282-be8c-a39be460d982@linaro.org> (raw)
In-Reply-To: <20250415192515.232910-67-richard.henderson@linaro.org>
On 4/15/25 12:23, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/aarch64/tcg-target-has.h | 2 -
> tcg/arm/tcg-target-has.h | 1 -
> tcg/i386/tcg-target-has.h | 2 -
> tcg/loongarch64/tcg-target-has.h | 2 -
> tcg/mips/tcg-target-has.h | 2 -
> tcg/ppc/tcg-target-has.h | 2 -
> tcg/riscv/tcg-target-has.h | 2 -
> tcg/s390x/tcg-target-has.h | 2 -
> tcg/sparc64/tcg-target-has.h | 2 -
> tcg/tcg-has.h | 1 -
> tcg/tci/tcg-target-has.h | 2 -
> tcg/tcg-op.c | 37 ++++++++++--------
> tcg/tcg.c | 8 ++--
> tcg/tci.c | 19 ++++-----
> tcg/aarch64/tcg-target.c.inc | 4 ++
> tcg/arm/tcg-target.c.inc | 4 ++
> tcg/i386/tcg-target.c.inc | 23 ++++++++---
> tcg/loongarch64/tcg-target.c.inc | 4 ++
> tcg/mips/tcg-target.c.inc | 4 ++
> tcg/ppc/tcg-target.c.inc | 26 ++++++++-----
> tcg/riscv/tcg-target.c.inc | 26 ++++++++-----
> tcg/s390x/tcg-target.c.inc | 66 +++++++++++++++-----------------
> tcg/sparc64/tcg-target.c.inc | 4 ++
> tcg/tci/tcg-target.c.inc | 19 +++++++--
> 24 files changed, 151 insertions(+), 113 deletions(-)
>
> diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h
> index 478d59676e..4f1840f44e 100644
> --- a/tcg/aarch64/tcg-target-has.h
> +++ b/tcg/aarch64/tcg-target-has.h
> @@ -15,7 +15,6 @@
> /* optional instructions */
> #define TCG_TARGET_HAS_bswap16_i32 1
> #define TCG_TARGET_HAS_bswap32_i32 1
> -#define TCG_TARGET_HAS_ctpop_i32 0
> #define TCG_TARGET_HAS_extract2_i32 1
> #define TCG_TARGET_HAS_negsetcond_i32 1
> #define TCG_TARGET_HAS_add2_i32 1
> @@ -28,7 +27,6 @@
> #define TCG_TARGET_HAS_bswap16_i64 1
> #define TCG_TARGET_HAS_bswap32_i64 1
> #define TCG_TARGET_HAS_bswap64_i64 1
> -#define TCG_TARGET_HAS_ctpop_i64 0
> #define TCG_TARGET_HAS_extract2_i64 1
> #define TCG_TARGET_HAS_negsetcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> diff --git a/tcg/arm/tcg-target-has.h b/tcg/arm/tcg-target-has.h
> index 1485a52c21..1cf3911613 100644
> --- a/tcg/arm/tcg-target-has.h
> +++ b/tcg/arm/tcg-target-has.h
> @@ -26,7 +26,6 @@ extern bool use_neon_instructions;
> /* optional instructions */
> #define TCG_TARGET_HAS_bswap16_i32 1
> #define TCG_TARGET_HAS_bswap32_i32 1
> -#define TCG_TARGET_HAS_ctpop_i32 0
> #define TCG_TARGET_HAS_extract2_i32 1
> #define TCG_TARGET_HAS_negsetcond_i32 1
> #define TCG_TARGET_HAS_mulu2_i32 1
> diff --git a/tcg/i386/tcg-target-has.h b/tcg/i386/tcg-target-has.h
> index b8a0a5c619..a71f8c7370 100644
> --- a/tcg/i386/tcg-target-has.h
> +++ b/tcg/i386/tcg-target-has.h
> @@ -28,7 +28,6 @@
> /* optional instructions */
> #define TCG_TARGET_HAS_bswap16_i32 1
> #define TCG_TARGET_HAS_bswap32_i32 1
> -#define TCG_TARGET_HAS_ctpop_i32 have_popcnt
> #define TCG_TARGET_HAS_extract2_i32 1
> #define TCG_TARGET_HAS_negsetcond_i32 1
> #define TCG_TARGET_HAS_add2_i32 1
> @@ -42,7 +41,6 @@
> #define TCG_TARGET_HAS_bswap16_i64 1
> #define TCG_TARGET_HAS_bswap32_i64 1
> #define TCG_TARGET_HAS_bswap64_i64 1
> -#define TCG_TARGET_HAS_ctpop_i64 have_popcnt
> #define TCG_TARGET_HAS_extract2_i64 1
> #define TCG_TARGET_HAS_negsetcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-has.h
> index f87d05efc6..33a1cf2326 100644
> --- a/tcg/loongarch64/tcg-target-has.h
> +++ b/tcg/loongarch64/tcg-target-has.h
> @@ -18,7 +18,6 @@
> #define TCG_TARGET_HAS_muls2_i32 0
> #define TCG_TARGET_HAS_bswap16_i32 1
> #define TCG_TARGET_HAS_bswap32_i32 1
> -#define TCG_TARGET_HAS_ctpop_i32 0
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> /* 64-bit operations */
> @@ -28,7 +27,6 @@
> #define TCG_TARGET_HAS_bswap16_i64 1
> #define TCG_TARGET_HAS_bswap32_i64 1
> #define TCG_TARGET_HAS_bswap64_i64 1
> -#define TCG_TARGET_HAS_ctpop_i64 0
> #define TCG_TARGET_HAS_add2_i64 0
> #define TCG_TARGET_HAS_sub2_i64 0
> #define TCG_TARGET_HAS_mulu2_i64 0
> diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h
> index ca33c9b745..470aa16452 100644
> --- a/tcg/mips/tcg-target-has.h
> +++ b/tcg/mips/tcg-target-has.h
> @@ -60,7 +60,6 @@ extern bool use_mips32r2_instructions;
>
> /* optional instructions detected at runtime */
> #define TCG_TARGET_HAS_extract2_i32 0
> -#define TCG_TARGET_HAS_ctpop_i32 0
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> #if TCG_TARGET_REG_BITS == 64
> @@ -68,7 +67,6 @@ extern bool use_mips32r2_instructions;
> #define TCG_TARGET_HAS_bswap32_i64 1
> #define TCG_TARGET_HAS_bswap64_i64 1
> #define TCG_TARGET_HAS_extract2_i64 0
> -#define TCG_TARGET_HAS_ctpop_i64 0
> #endif
>
> #define TCG_TARGET_HAS_qemu_ldst_i128 0
> diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h
> index 2b381b99a2..f071435d98 100644
> --- a/tcg/ppc/tcg-target-has.h
> +++ b/tcg/ppc/tcg-target-has.h
> @@ -19,7 +19,6 @@
> /* optional instructions */
> #define TCG_TARGET_HAS_bswap16_i32 1
> #define TCG_TARGET_HAS_bswap32_i32 1
> -#define TCG_TARGET_HAS_ctpop_i32 have_isa_2_06
> #define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_negsetcond_i32 1
> #define TCG_TARGET_HAS_mulu2_i32 0
> @@ -33,7 +32,6 @@
> #define TCG_TARGET_HAS_bswap16_i64 1
> #define TCG_TARGET_HAS_bswap32_i64 1
> #define TCG_TARGET_HAS_bswap64_i64 1
> -#define TCG_TARGET_HAS_ctpop_i64 have_isa_2_06
> #define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_negsetcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h
> index 385a6736c0..a3b634570b 100644
> --- a/tcg/riscv/tcg-target-has.h
> +++ b/tcg/riscv/tcg-target-has.h
> @@ -18,7 +18,6 @@
> #define TCG_TARGET_HAS_muls2_i32 0
> #define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB)
> #define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB)
> -#define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB)
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> #define TCG_TARGET_HAS_negsetcond_i64 1
> @@ -27,7 +26,6 @@
> #define TCG_TARGET_HAS_bswap16_i64 (cpuinfo & CPUINFO_ZBB)
> #define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB)
> #define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB)
> -#define TCG_TARGET_HAS_ctpop_i64 (cpuinfo & CPUINFO_ZBB)
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> #define TCG_TARGET_HAS_mulu2_i64 0
> diff --git a/tcg/s390x/tcg-target-has.h b/tcg/s390x/tcg-target-has.h
> index 0794394fea..87f117ce58 100644
> --- a/tcg/s390x/tcg-target-has.h
> +++ b/tcg/s390x/tcg-target-has.h
> @@ -31,7 +31,6 @@ extern uint64_t s390_facilities[3];
> /* optional instructions */
> #define TCG_TARGET_HAS_bswap16_i32 1
> #define TCG_TARGET_HAS_bswap32_i32 1
> -#define TCG_TARGET_HAS_ctpop_i32 1
> #define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_negsetcond_i32 1
> #define TCG_TARGET_HAS_add2_i32 1
> @@ -44,7 +43,6 @@ extern uint64_t s390_facilities[3];
> #define TCG_TARGET_HAS_bswap16_i64 1
> #define TCG_TARGET_HAS_bswap32_i64 1
> #define TCG_TARGET_HAS_bswap64_i64 1
> -#define TCG_TARGET_HAS_ctpop_i64 1
> #define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_negsetcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> diff --git a/tcg/sparc64/tcg-target-has.h b/tcg/sparc64/tcg-target-has.h
> index 56262640ff..40e54e1543 100644
> --- a/tcg/sparc64/tcg-target-has.h
> +++ b/tcg/sparc64/tcg-target-has.h
> @@ -16,7 +16,6 @@ extern bool use_vis3_instructions;
> /* optional instructions */
> #define TCG_TARGET_HAS_bswap16_i32 0
> #define TCG_TARGET_HAS_bswap32_i32 0
> -#define TCG_TARGET_HAS_ctpop_i32 0
> #define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_negsetcond_i32 1
> #define TCG_TARGET_HAS_add2_i32 1
> @@ -29,7 +28,6 @@ extern bool use_vis3_instructions;
> #define TCG_TARGET_HAS_bswap16_i64 0
> #define TCG_TARGET_HAS_bswap32_i64 0
> #define TCG_TARGET_HAS_bswap64_i64 0
> -#define TCG_TARGET_HAS_ctpop_i64 0
> #define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_negsetcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> diff --git a/tcg/tcg-has.h b/tcg/tcg-has.h
> index 6bba845944..97f4e83303 100644
> --- a/tcg/tcg-has.h
> +++ b/tcg/tcg-has.h
> @@ -15,7 +15,6 @@
> #define TCG_TARGET_HAS_bswap16_i64 0
> #define TCG_TARGET_HAS_bswap32_i64 0
> #define TCG_TARGET_HAS_bswap64_i64 0
> -#define TCG_TARGET_HAS_ctpop_i64 0
> #define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_negsetcond_i64 0
> #define TCG_TARGET_HAS_add2_i64 0
> diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h
> index daa6db4799..774fb149fc 100644
> --- a/tcg/tci/tcg-target-has.h
> +++ b/tcg/tci/tcg-target-has.h
> @@ -10,7 +10,6 @@
> #define TCG_TARGET_HAS_bswap16_i32 1
> #define TCG_TARGET_HAS_bswap32_i32 1
> #define TCG_TARGET_HAS_extract2_i32 0
> -#define TCG_TARGET_HAS_ctpop_i32 1
> #define TCG_TARGET_HAS_negsetcond_i32 0
> #define TCG_TARGET_HAS_muls2_i32 1
> #define TCG_TARGET_HAS_qemu_st8_i32 0
> @@ -21,7 +20,6 @@
> #define TCG_TARGET_HAS_bswap32_i64 1
> #define TCG_TARGET_HAS_bswap64_i64 1
> #define TCG_TARGET_HAS_extract2_i64 0
> -#define TCG_TARGET_HAS_ctpop_i64 1
> #define TCG_TARGET_HAS_negsetcond_i64 0
> #define TCG_TARGET_HAS_muls2_i64 1
> #define TCG_TARGET_HAS_add2_i32 1
> diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
> index 7bf7de1213..db0e79059b 100644
> --- a/tcg/tcg-op.c
> +++ b/tcg/tcg-op.c
> @@ -765,7 +765,8 @@ void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
> tcg_temp_free_i64(t2);
> return;
> }
> - if (TCG_TARGET_HAS_ctpop_i32 || TCG_TARGET_HAS_ctpop_i64) {
> + if (tcg_op_supported(INDEX_op_ctpop_i32, TCG_TYPE_I32, 0) ||
> + tcg_op_supported(INDEX_op_ctpop_i64, TCG_TYPE_I64, 0)) {
> t = tcg_temp_ebb_new_i32();
> tcg_gen_subi_i32(t, arg1, 1);
> tcg_gen_andc_i32(t, t, arg1);
> @@ -788,8 +789,9 @@ void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
>
> void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
> {
> - if (!tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0)
> - && TCG_TARGET_HAS_ctpop_i32 && arg2 == 32) {
> + if (arg2 == 32
> + && !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0)
> + && tcg_op_supported(INDEX_op_ctpop_i32, TCG_TYPE_I32, 0)) {
> /* This equivalence has the advantage of not requiring a fixup. */
> TCGv_i32 t = tcg_temp_ebb_new_i32();
> tcg_gen_subi_i32(t, arg1, 1);
> @@ -817,9 +819,9 @@ void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg)
>
> void tcg_gen_ctpop_i32(TCGv_i32 ret, TCGv_i32 arg1)
> {
> - if (TCG_TARGET_HAS_ctpop_i32) {
> + if (tcg_op_supported(INDEX_op_ctpop_i32, TCG_TYPE_I32, 0)) {
> tcg_gen_op2_i32(INDEX_op_ctpop_i32, ret, arg1);
> - } else if (TCG_TARGET_HAS_ctpop_i64) {
> + } else if (tcg_op_supported(INDEX_op_ctpop_i64, TCG_TYPE_I64, 0)) {
> TCGv_i64 t = tcg_temp_ebb_new_i64();
> tcg_gen_extu_i32_i64(t, arg1);
> tcg_gen_ctpop_i64(t, t);
> @@ -2370,7 +2372,7 @@ void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
> tcg_gen_op3_i64(INDEX_op_ctz, ret, arg1, arg2);
> return;
> }
> - if (TCG_TARGET_HAS_ctpop_i64) {
> + if (tcg_op_supported(INDEX_op_ctpop_i64, TCG_TYPE_I64, 0)) {
> t = tcg_temp_ebb_new_i64();
> tcg_gen_subi_i64(t, arg1, 1);
> tcg_gen_andc_i64(t, t, arg1);
> @@ -2404,7 +2406,7 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
> tcg_temp_free_i32(t32);
> } else if (arg2 == 64
> && !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0)
> - && TCG_TARGET_HAS_ctpop_i64) {
> + && tcg_op_supported(INDEX_op_ctpop_i64, TCG_TYPE_I64, 0)) {
> /* This equivalence has the advantage of not requiring a fixup. */
> TCGv_i64 t = tcg_temp_ebb_new_i64();
> tcg_gen_subi_i64(t, arg1, 1);
> @@ -2432,16 +2434,21 @@ void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg)
>
> void tcg_gen_ctpop_i64(TCGv_i64 ret, TCGv_i64 arg1)
> {
> - if (TCG_TARGET_HAS_ctpop_i64) {
> - tcg_gen_op2_i64(INDEX_op_ctpop_i64, ret, arg1);
> - } else if (TCG_TARGET_REG_BITS == 32 && TCG_TARGET_HAS_ctpop_i32) {
> - tcg_gen_ctpop_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
> - tcg_gen_ctpop_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
> - tcg_gen_add_i32(TCGV_LOW(ret), TCGV_LOW(ret), TCGV_HIGH(ret));
> - tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
> + if (TCG_TARGET_REG_BITS == 64) {
> + if (tcg_op_supported(INDEX_op_ctpop_i64, TCG_TYPE_I64, 0)) {
> + tcg_gen_op2_i64(INDEX_op_ctpop_i64, ret, arg1);
> + return;
> + }
> } else {
> - gen_helper_ctpop_i64(ret, arg1);
> + if (tcg_op_supported(INDEX_op_ctpop_i32, TCG_TYPE_I32, 0)) {
> + tcg_gen_ctpop_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
> + tcg_gen_ctpop_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
> + tcg_gen_add_i32(TCGV_LOW(ret), TCGV_LOW(ret), TCGV_HIGH(ret));
> + tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
> + return;
> + }
> }
> + gen_helper_ctpop_i64(ret, arg1);
> }
>
> void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 4029b01bee..8344aee6c1 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -1027,6 +1027,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
> OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and),
> OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
> OUTOP(INDEX_op_clz, TCGOutOpBinary, outop_clz),
> + OUTOP(INDEX_op_ctpop_i32, TCGOutOpUnary, outop_ctpop),
> + OUTOP(INDEX_op_ctpop_i64, TCGOutOpUnary, outop_ctpop),
> OUTOP(INDEX_op_ctz, TCGOutOpBinary, outop_ctz),
> OUTOP(INDEX_op_divs, TCGOutOpBinary, outop_divs),
> OUTOP(INDEX_op_divu, TCGOutOpBinary, outop_divu),
> @@ -2290,8 +2292,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
> return TCG_TARGET_HAS_bswap16_i32;
> case INDEX_op_bswap32_i32:
> return TCG_TARGET_HAS_bswap32_i32;
> - case INDEX_op_ctpop_i32:
> - return TCG_TARGET_HAS_ctpop_i32;
>
> case INDEX_op_brcond2_i32:
> case INDEX_op_setcond2_i32:
> @@ -2331,8 +2331,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
> return TCG_TARGET_HAS_bswap32_i64;
> case INDEX_op_bswap64_i64:
> return TCG_TARGET_HAS_bswap64_i64;
> - case INDEX_op_ctpop_i64:
> - return TCG_TARGET_HAS_ctpop_i64;
> case INDEX_op_add2_i64:
> return TCG_TARGET_HAS_add2_i64;
> case INDEX_op_sub2_i64:
> @@ -5446,6 +5444,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
> }
> break;
>
> + case INDEX_op_ctpop_i32:
> + case INDEX_op_ctpop_i64:
> case INDEX_op_neg:
> case INDEX_op_not:
> {
> diff --git a/tcg/tci.c b/tcg/tci.c
> index 550f2014a8..8bcf48b251 100644
> --- a/tcg/tci.c
> +++ b/tcg/tci.c
> @@ -26,6 +26,8 @@
> #include <ffi.h>
>
>
> +#define ctpop_tr glue(ctpop, TCG_TARGET_REG_BITS)
> +
> /*
> * Enable TCI assertions only when debugging TCG (and without NDEBUG defined).
> * Without assertions, the interpreter runs much faster.
> @@ -575,6 +577,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
> tci_args_rr(insn, &r0, &r1);
> regs[r0] = ~regs[r1];
> break;
> + case INDEX_op_ctpop_i32:
> + case INDEX_op_ctpop_i64:
> + tci_args_rr(insn, &r0, &r1);
> + regs[r0] = ctpop_tr(regs[r1]);
> + break;
>
> /* Arithmetic operations (32 bit). */
>
> @@ -604,12 +611,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
> tmp32 = regs[r1];
> regs[r0] = tmp32 ? ctz32(tmp32) : regs[r2];
> break;
> -#if TCG_TARGET_HAS_ctpop_i32
> - case INDEX_op_ctpop_i32:
> - tci_args_rr(insn, &r0, &r1);
> - regs[r0] = ctpop32(regs[r1]);
> - break;
> -#endif
>
> /* Shift/rotate operations. */
>
> @@ -739,12 +740,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
> tci_args_rrr(insn, &r0, &r1, &r2);
> regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2];
> break;
> -#if TCG_TARGET_HAS_ctpop_i64
> - case INDEX_op_ctpop_i64:
> - tci_args_rr(insn, &r0, &r1);
> - regs[r0] = ctpop64(regs[r1]);
> - break;
> -#endif
> #if TCG_TARGET_HAS_mulu2_i64
> case INDEX_op_mulu2_i64:
> tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
> diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
> index 8441c5f4bf..0f01fa8c20 100644
> --- a/tcg/aarch64/tcg-target.c.inc
> +++ b/tcg/aarch64/tcg-target.c.inc
> @@ -2129,6 +2129,10 @@ static const TCGOutOpBinary outop_clz = {
> .out_rri = tgen_clzi,
> };
>
> +static const TCGOutOpUnary outop_ctpop = {
> + .base.static_constraint = C_NotImplemented,
> +};
> +
> static void tgen_ctz(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
> index c05f21c82c..e109c65965 100644
> --- a/tcg/arm/tcg-target.c.inc
> +++ b/tcg/arm/tcg-target.c.inc
> @@ -1888,6 +1888,10 @@ static const TCGOutOpBinary outop_clz = {
> .out_rri = tgen_clzi,
> };
>
> +static const TCGOutOpUnary outop_ctpop = {
> + .base.static_constraint = C_NotImplemented,
> +};
> +
> static void tgen_ctz(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
> index f7d0b93af0..318a30ebe0 100644
> --- a/tcg/i386/tcg-target.c.inc
> +++ b/tcg/i386/tcg-target.c.inc
> @@ -2628,6 +2628,23 @@ static const TCGOutOpBinary outop_clz = {
> .out_rri = tgen_clzi,
> };
>
> +static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> +{
> + int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW;
> + tcg_out_modrm(s, OPC_POPCNT + rexw, a0, a1);
> +}
> +
> +static TCGConstraintSetIndex cset_ctpop(TCGType type, unsigned flags)
> +{
> + return have_popcnt ? C_O1_I1(r, r) : C_NotImplemented;
> +}
> +
> +static const TCGOutOpUnary outop_ctpop = {
> + .base.static_constraint = C_Dynamic,
> + .base.dynamic_constraint = cset_ctpop,
> + .out_rr = tgen_ctpop,
> +};
> +
> static void tgen_ctz(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -3046,10 +3063,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> }
> break;
>
> - OP_32_64(ctpop):
> - tcg_out_modrm(s, OPC_POPCNT + rexw, a0, a1);
> - break;
> -
> OP_32_64(brcond):
> tcg_out_brcond(s, rexw, a2, a0, a1, const_args[1],
> arg_label(args[3]), 0);
> @@ -3893,8 +3906,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_extract_i64:
> case INDEX_op_sextract_i32:
> case INDEX_op_sextract_i64:
> - case INDEX_op_ctpop_i32:
> - case INDEX_op_ctpop_i64:
> return C_O1_I1(r, r);
>
> case INDEX_op_extract2_i32:
> diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
> index ea0a92ece9..41a4f6e2ea 100644
> --- a/tcg/loongarch64/tcg-target.c.inc
> +++ b/tcg/loongarch64/tcg-target.c.inc
> @@ -1321,6 +1321,10 @@ static const TCGOutOpBinary outop_clz = {
> .out_rri = tgen_clzi,
> };
>
> +static const TCGOutOpUnary outop_ctpop = {
> + .base.static_constraint = C_NotImplemented,
> +};
> +
> static void tgen_ctzi(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, tcg_target_long a2)
> {
> diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
> index e8720b63ed..a94c965046 100644
> --- a/tcg/mips/tcg-target.c.inc
> +++ b/tcg/mips/tcg-target.c.inc
> @@ -1734,6 +1734,10 @@ static const TCGOutOpBinary outop_clz = {
> .out_rri = tgen_clzi,
> };
>
> +static const TCGOutOpUnary outop_ctpop = {
> + .base.static_constraint = C_NotImplemented,
> +};
> +
> static const TCGOutOpBinary outop_ctz = {
> .base.static_constraint = C_NotImplemented,
> };
> diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
> index 2cdabcf610..ab56c623c7 100644
> --- a/tcg/ppc/tcg-target.c.inc
> +++ b/tcg/ppc/tcg-target.c.inc
> @@ -2974,6 +2974,23 @@ static const TCGOutOpBinary outop_clz = {
> .out_rri = tgen_clzi,
> };
>
> +static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> +{
> + uint32_t insn = type == TCG_TYPE_I32 ? CNTPOPW : CNTPOPD;
> + tcg_out32(s, insn | SAB(a1, a0, 0));
> +}
> +
> +static TCGConstraintSetIndex cset_ctpop(TCGType type, unsigned flags)
> +{
> + return have_isa_2_06 ? C_O1_I1(r, r) : C_NotImplemented;
> +}
> +
> +static const TCGOutOpUnary outop_ctpop = {
> + .base.static_constraint = C_Dynamic,
> + .base.dynamic_constraint = cset_ctpop,
> + .out_rr = tgen_ctpop,
> +};
> +
> static void tgen_ctz(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -3396,13 +3413,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
> break;
>
> - case INDEX_op_ctpop_i32:
> - tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0));
> - break;
> - case INDEX_op_ctpop_i64:
> - tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0));
> - break;
> -
> case INDEX_op_brcond_i32:
> tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
> arg_label(args[3]), TCG_TYPE_I32);
> @@ -4226,7 +4236,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_ld16u_i32:
> case INDEX_op_ld16s_i32:
> case INDEX_op_ld_i32:
> - case INDEX_op_ctpop_i32:
> case INDEX_op_bswap16_i32:
> case INDEX_op_bswap32_i32:
> case INDEX_op_extract_i32:
> @@ -4238,7 +4247,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_ld32u_i64:
> case INDEX_op_ld32s_i64:
> case INDEX_op_ld_i64:
> - case INDEX_op_ctpop_i64:
> case INDEX_op_ext_i32_i64:
> case INDEX_op_extu_i32_i64:
> case INDEX_op_bswap16_i64:
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 1ceb1aeb1c..a5cd18c99e 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -2023,6 +2023,23 @@ static const TCGOutOpBinary outop_clz = {
> .out_rri = tgen_clzi,
> };
>
> +static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> +{
> + RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_CPOPW : OPC_CPOP;
> + tcg_out_opc_imm(s, insn, a0, a1, 0);
> +}
> +
> +static TCGConstraintSetIndex cset_ctpop(TCGType type, unsigned flags)
> +{
> + return cpuinfo & CPUINFO_ZBB ? C_O1_I1(r, r) : C_NotImplemented;
> +}
> +
> +static const TCGOutOpUnary outop_ctpop = {
> + .base.static_constraint = C_Dynamic,
> + .base.dynamic_constraint = cset_ctpop,
> + .out_rr = tgen_ctpop,
> +};
> +
> static void tgen_ctz(TCGContext *s, TCGType type,
> TCGReg a0, TCGReg a1, TCGReg a2)
> {
> @@ -2438,13 +2455,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> }
> break;
>
> - case INDEX_op_ctpop_i32:
> - tcg_out_opc_imm(s, OPC_CPOPW, a0, a1, 0);
> - break;
> - case INDEX_op_ctpop_i64:
> - tcg_out_opc_imm(s, OPC_CPOP, a0, a1, 0);
> - break;
> -
> case INDEX_op_add2_i32:
> tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
> const_args[4], const_args[5], false, true);
> @@ -2808,8 +2818,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_bswap16_i64:
> case INDEX_op_bswap32_i64:
> case INDEX_op_bswap64_i64:
> - case INDEX_op_ctpop_i32:
> - case INDEX_op_ctpop_i64:
> return C_O1_I1(r, r);
>
> case INDEX_op_st8_i32:
> diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
> index 374136ed14..71adb0964d 100644
> --- a/tcg/s390x/tcg-target.c.inc
> +++ b/tcg/s390x/tcg-target.c.inc
> @@ -1514,32 +1514,6 @@ static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
> tgen_movcond_int(s, type, dest, v3, v3const, v4, cc, inv_cc);
> }
>
> -static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
> -{
> - /* With MIE3, and bit 0 of m4 set, we get the complete result. */
> - if (HAVE_FACILITY(MISC_INSN_EXT3)) {
> - if (type == TCG_TYPE_I32) {
> - tcg_out_ext32u(s, dest, src);
> - src = dest;
> - }
> - tcg_out_insn(s, RRFc, POPCNT, dest, src, 8);
> - return;
> - }
> -
> - /* Without MIE3, each byte gets the count of bits for the byte. */
> - tcg_out_insn(s, RRFc, POPCNT, dest, src, 0);
> -
> - /* Multiply to sum each byte at the top of the word. */
> - if (type == TCG_TYPE_I32) {
> - tcg_out_insn(s, RIL, MSFI, dest, 0x01010101);
> - tcg_out_sh32(s, RS_SRL, dest, TCG_REG_NONE, 24);
> - } else {
> - tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0x0101010101010101ull);
> - tcg_out_insn(s, RRE, MSGR, dest, TCG_TMP0);
> - tcg_out_sh64(s, RSY_SRLG, dest, dest, TCG_REG_NONE, 56);
> - }
> -}
> -
> static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
> int ofs, int len, int z)
> {
> @@ -2268,6 +2242,37 @@ static const TCGOutOpBinary outop_clz = {
> .out_rri = tgen_clzi,
> };
>
> +static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
> +{
> + /* With MIE3, and bit 0 of m4 set, we get the complete result. */
> + if (HAVE_FACILITY(MISC_INSN_EXT3)) {
> + if (type == TCG_TYPE_I32) {
> + tcg_out_ext32u(s, dest, src);
> + src = dest;
> + }
> + tcg_out_insn(s, RRFc, POPCNT, dest, src, 8);
> + return;
> + }
> +
> + /* Without MIE3, each byte gets the count of bits for the byte. */
> + tcg_out_insn(s, RRFc, POPCNT, dest, src, 0);
> +
> + /* Multiply to sum each byte at the top of the word. */
> + if (type == TCG_TYPE_I32) {
> + tcg_out_insn(s, RIL, MSFI, dest, 0x01010101);
> + tcg_out_sh32(s, RS_SRL, dest, TCG_REG_NONE, 24);
> + } else {
> + tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0x0101010101010101ull);
> + tcg_out_insn(s, RRE, MSGR, dest, TCG_TMP0);
> + tcg_out_sh64(s, RSY_SRLG, dest, dest, TCG_REG_NONE, 56);
> + }
> +}
> +
> +static const TCGOutOpUnary outop_ctpop = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_ctpop,
> +};
> +
> static const TCGOutOpBinary outop_ctz = {
> .base.static_constraint = C_NotImplemented,
> };
> @@ -2914,13 +2919,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tgen_sextract(s, args[0], args[1], args[2], args[3]);
> break;
>
> - case INDEX_op_ctpop_i32:
> - tgen_ctpop(s, TCG_TYPE_I32, args[0], args[1]);
> - break;
> - case INDEX_op_ctpop_i64:
> - tgen_ctpop(s, TCG_TYPE_I64, args[0], args[1]);
> - break;
> -
> case INDEX_op_mb:
> /* The host memory model is quite strong, we simply need to
> serialize the instruction stream. */
> @@ -3429,8 +3427,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_extract_i64:
> case INDEX_op_sextract_i32:
> case INDEX_op_sextract_i64:
> - case INDEX_op_ctpop_i32:
> - case INDEX_op_ctpop_i64:
> return C_O1_I1(r, r);
>
> case INDEX_op_qemu_ld_i32:
> diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
> index a9257b8b93..43ca23f593 100644
> --- a/tcg/sparc64/tcg-target.c.inc
> +++ b/tcg/sparc64/tcg-target.c.inc
> @@ -1322,6 +1322,10 @@ static const TCGOutOpBinary outop_clz = {
> .base.static_constraint = C_NotImplemented,
> };
>
> +static const TCGOutOpUnary outop_ctpop = {
> + .base.static_constraint = C_NotImplemented,
> +};
> +
> static const TCGOutOpBinary outop_ctz = {
> .base.static_constraint = C_NotImplemented,
> };
> diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
> index d8d45e2c4b..a931369a80 100644
> --- a/tcg/tci/tcg-target.c.inc
> +++ b/tcg/tci/tcg-target.c.inc
> @@ -66,8 +66,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_extract_i64:
> case INDEX_op_sextract_i32:
> case INDEX_op_sextract_i64:
> - case INDEX_op_ctpop_i32:
> - case INDEX_op_ctpop_i64:
> return C_O1_I1(r, r);
>
> case INDEX_op_st8_i32:
> @@ -883,6 +881,22 @@ static const TCGOutOpBinary outop_xor = {
> .out_rrr = tgen_xor,
> };
>
> +static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> +{
> + tcg_out_op_rr(s, glue(INDEX_op_ctpop_i,TCG_TARGET_REG_BITS), a0, a1);
> +}
> +
> +static TCGConstraintSetIndex cset_ctpop(TCGType type, unsigned flags)
> +{
> + return type == TCG_TYPE_REG ? C_O1_I1(r, r) : C_NotImplemented;
> +}
> +
> +static const TCGOutOpUnary outop_ctpop = {
> + .base.static_constraint = C_Dynamic,
> + .base.dynamic_constraint = cset_ctpop,
> + .out_rr = tgen_ctpop,
> +};
> +
> static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
> {
> tcg_out_op_rr(s, INDEX_op_neg, a0, a1);
> @@ -961,7 +975,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_op_rl(s, opc, TCG_REG_TMP, arg_label(args[3]));
> break;
>
> - CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */
> case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */
> case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */
> tcg_out_op_rr(s, opc, args[0], args[1]);
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
next prev parent reply other threads:[~2025-04-15 21:15 UTC|newest]
Thread overview: 316+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-15 19:22 [PATCH v4 000/163] tcg: Convert to TCGOutOp structures Richard Henderson
2025-04-15 19:22 ` [PATCH v4 001/163] tcg: Add all_outop[] Richard Henderson
2025-04-15 19:22 ` [PATCH v4 002/163] tcg: Use extract2 for cross-word 64-bit extract on 32-bit host Richard Henderson
2025-04-15 19:22 ` [PATCH v4 003/163] tcg: Remove INDEX_op_ext{8,16,32}* Richard Henderson
2025-04-15 19:22 ` [PATCH v4 004/163] tcg: Merge INDEX_op_mov_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 005/163] tcg: Convert add to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 006/163] tcg: Merge INDEX_op_add_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 007/163] tcg: Convert and to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 008/163] tcg: Merge INDEX_op_and_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 009/163] tcg/optimize: Fold andc with immediate to and Richard Henderson
2025-04-15 19:22 ` [PATCH v4 010/163] tcg/optimize: Emit add r, r, -1 in fold_setcond_tst_pow2 Richard Henderson
2025-04-15 19:22 ` [PATCH v4 011/163] tcg: Convert andc to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 012/163] tcg: Merge INDEX_op_andc_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 013/163] tcg: Convert or to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 014/163] tcg: Merge INDEX_op_or_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 015/163] tcg/optimize: Fold orc with immediate to or Richard Henderson
2025-04-15 19:22 ` [PATCH v4 016/163] tcg: Convert orc to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 017/163] tcg: Merge INDEX_op_orc_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 018/163] tcg: Convert xor to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 019/163] tcg: Merge INDEX_op_xor_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 020/163] tcg/optimize: Fold eqv with immediate to xor Richard Henderson
2025-04-15 19:22 ` [PATCH v4 021/163] tcg: Convert eqv to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 022/163] tcg: Merge INDEX_op_eqv_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 023/163] tcg: Convert nand to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 024/163] tcg: Merge INDEX_op_nand_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 025/163] tcg/loongarch64: Do not accept constant argument to nor Richard Henderson
2025-04-15 19:22 ` [PATCH v4 026/163] tcg: Convert nor to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 027/163] tcg: Merge INDEX_op_nor_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 028/163] tcg/arm: Fix constraints for sub Richard Henderson
2025-04-15 19:23 ` [PATCH v4 029/163] tcg: Convert sub to TCGOutOpSubtract Richard Henderson
2025-04-15 21:00 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 030/163] tcg: Merge INDEX_op_sub_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 031/163] tcg: Convert neg to TCGOutOpUnary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 032/163] tcg: Merge INDEX_op_neg_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 033/163] tcg: Convert not to TCGOutOpUnary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 034/163] tcg: Merge INDEX_op_not_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 035/163] tcg: Convert mul to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 036/163] tcg: Merge INDEX_op_mul_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 037/163] tcg: Convert muluh to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 038/163] tcg: Merge INDEX_op_muluh_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 039/163] tcg: Convert mulsh to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 040/163] tcg: Merge INDEX_op_mulsh_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 041/163] tcg: Convert div to TCGOutOpBinary Richard Henderson
2025-04-15 21:02 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 042/163] tcg: Merge INDEX_op_div_{i32,i64} Richard Henderson
2025-04-15 21:04 ` Pierrick Bouvier
2025-04-22 15:27 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 043/163] tcg: Convert divu to TCGOutOpBinary Richard Henderson
2025-04-15 21:04 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 044/163] tcg: Merge INDEX_op_divu_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 045/163] tcg: Convert div2 to TCGOutOpDivRem Richard Henderson
2025-04-15 19:23 ` [PATCH v4 046/163] tcg: Merge INDEX_op_div2_{i32,i64} Richard Henderson
2025-04-15 21:05 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 047/163] tcg: Convert divu2 to TCGOutOpDivRem Richard Henderson
2025-04-15 21:05 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 048/163] tcg: Merge INDEX_op_divu2_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 049/163] tcg: Convert rem to TCGOutOpBinary Richard Henderson
2025-04-15 21:06 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 050/163] tcg: Merge INDEX_op_rem_{i32,i64} Richard Henderson
2025-04-15 21:06 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 051/163] tcg: Convert remu to TCGOutOpBinary Richard Henderson
2025-04-15 21:07 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 052/163] tcg: Merge INDEX_op_remu_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 053/163] tcg: Convert shl to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 054/163] tcg: Merge INDEX_op_shl_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 055/163] tcg: Convert shr to TCGOutOpBinary Richard Henderson
2025-04-15 21:08 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 056/163] tcg: Merge INDEX_op_shr_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 057/163] tcg: Convert sar to TCGOutOpBinary Richard Henderson
2025-04-15 21:09 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 058/163] tcg: Merge INDEX_op_sar_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 059/163] tcg: Do not require both rotr and rotl from the backend Richard Henderson
2025-04-15 21:10 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 060/163] tcg: Convert rotl, rotr to TCGOutOpBinary Richard Henderson
2025-04-15 21:10 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 061/163] tcg: Merge INDEX_op_rot{l,r}_{i32,i64} Richard Henderson
2025-04-15 21:11 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 062/163] tcg: Convert clz to TCGOutOpBinary Richard Henderson
2025-04-15 21:12 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 063/163] tcg: Merge INDEX_op_clz_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 064/163] tcg: Convert ctz to TCGOutOpBinary Richard Henderson
2025-04-15 21:13 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 065/163] tcg: Merge INDEX_op_ctz_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 066/163] tcg: Convert ctpop to TCGOutOpUnary Richard Henderson
2025-04-15 21:14 ` Pierrick Bouvier [this message]
2025-04-15 19:23 ` [PATCH v4 067/163] tcg: Merge INDEX_op_ctpop_{i32,i64} Richard Henderson
2025-04-15 21:15 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 068/163] tcg: Convert muls2 to TCGOutOpMul2 Richard Henderson
2025-04-15 21:17 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 069/163] tcg: Merge INDEX_op_muls2_{i32,i64} Richard Henderson
2025-04-15 21:17 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 070/163] tcg: Convert mulu2 to TCGOutOpMul2 Richard Henderson
2025-04-15 21:18 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 071/163] tcg: Merge INDEX_op_mulu2_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 072/163] tcg/loongarch64: Support negsetcond Richard Henderson
2025-04-15 21:19 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 073/163] tcg/mips: " Richard Henderson
2025-04-15 21:20 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 074/163] tcg/tci: " Richard Henderson
2025-04-15 21:20 ` Pierrick Bouvier
2025-04-22 15:28 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 075/163] tcg: Remove TCG_TARGET_HAS_negsetcond_{i32,i64} Richard Henderson
2025-04-22 15:35 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 076/163] tcg: Convert setcond, negsetcond to TCGOutOpSetcond Richard Henderson
2025-04-15 21:21 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 077/163] tcg: Merge INDEX_op_{neg}setcond_{i32,i64}` Richard Henderson
2025-04-15 21:22 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 078/163] tcg: Convert brcond to TCGOutOpBrcond Richard Henderson
2025-04-15 21:23 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 079/163] tcg: Merge INDEX_op_brcond_{i32,i64} Richard Henderson
2025-04-15 21:24 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 080/163] tcg: Convert movcond to TCGOutOpMovcond Richard Henderson
2025-04-15 21:25 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 081/163] tcg: Merge INDEX_op_movcond_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 082/163] tcg/ppc: Drop fallback constant loading in tcg_out_cmp Richard Henderson
2025-04-15 21:26 ` Pierrick Bouvier
2025-04-16 14:39 ` Nicholas Piggin
2025-04-16 18:57 ` Richard Henderson
2025-04-15 19:23 ` [PATCH v4 083/163] tcg/arm: Expand arguments to tcg_out_cmp2 Richard Henderson
2025-04-15 21:27 ` Pierrick Bouvier
2025-04-22 15:37 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 084/163] tcg/ppc: " Richard Henderson
2025-04-15 21:27 ` Pierrick Bouvier
2025-04-16 14:43 ` Nicholas Piggin
2025-04-22 15:37 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 085/163] tcg: Convert brcond2_i32 to TCGOutOpBrcond2 Richard Henderson
2025-04-15 21:37 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 086/163] tcg: Convert setcond2_i32 to TCGOutOpSetcond2 Richard Henderson
2025-04-15 21:39 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 087/163] tcg: Convert bswap16 to TCGOutOpBswap Richard Henderson
2025-04-15 21:40 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 088/163] tcg: Merge INDEX_op_bswap16_{i32,i64} Richard Henderson
2025-04-15 21:41 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 089/163] tcg: Convert bswap32 to TCGOutOpBswap Richard Henderson
2025-04-15 21:46 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 090/163] tcg: Merge INDEX_op_bswap32_{i32,i64} Richard Henderson
2025-04-15 21:47 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 091/163] tcg: Convert bswap64 to TCGOutOpUnary Richard Henderson
2025-04-15 21:48 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 092/163] tcg: Rename INDEX_op_bswap64_i64 to INDEX_op_bswap64 Richard Henderson
2025-04-15 21:48 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 093/163] tcg: Convert extract to TCGOutOpExtract Richard Henderson
2025-04-15 21:50 ` Pierrick Bouvier
2025-06-09 13:52 ` Andrea Bolognani
2025-06-26 16:20 ` Andrea Bolognani
2025-06-27 13:16 ` Richard Henderson
2025-06-27 14:29 ` Philippe Mathieu-Daudé
2025-06-30 12:08 ` Andrea Bolognani
2025-04-15 19:24 ` [PATCH v4 094/163] tcg: Merge INDEX_op_extract_{i32,i64} Richard Henderson
2025-04-15 21:51 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 095/163] tcg: Convert sextract to TCGOutOpExtract Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 096/163] tcg: Merge INDEX_op_sextract_{i32,i64} Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 097/163] tcg: Convert ext_i32_i64 to TCGOutOpUnary Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 098/163] tcg: Convert extu_i32_i64 " Richard Henderson
2025-04-15 21:56 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 099/163] tcg: Convert extrl_i64_i32 " Richard Henderson
2025-04-15 21:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 100/163] tcg: Convert extrh_i64_i32 " Richard Henderson
2025-04-15 21:58 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 101/163] tcg: Convert deposit to TCGOutOpDeposit Richard Henderson
2025-04-15 21:59 ` Pierrick Bouvier
2025-08-28 7:37 ` Michael Tokarev
2025-04-15 19:24 ` [PATCH v4 102/163] tcg/aarch64: Improve deposit Richard Henderson
2025-04-15 22:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 103/163] tcg: Merge INDEX_op_deposit_{i32,i64} Richard Henderson
2025-04-15 19:24 ` [PATCH v4 104/163] tcg: Convert extract2 to TCGOutOpExtract2 Richard Henderson
2025-04-15 22:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 105/163] tcg: Merge INDEX_op_extract2_{i32,i64} Richard Henderson
2025-04-15 22:02 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 106/163] tcg: Expand fallback add2 with 32-bit operations Richard Henderson
2025-04-15 22:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 107/163] tcg: Expand fallback sub2 " Richard Henderson
2025-04-15 22:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 108/163] tcg: Do not default add2/sub2_i32 for 32-bit hosts Richard Henderson
2025-04-15 22:04 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 109/163] tcg/mips: Drop support for add2/sub2 Richard Henderson
2025-04-15 22:04 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 110/163] tcg/riscv: " Richard Henderson
2025-04-15 22:05 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 111/163] tcg: Move i into each for loop in liveness_pass_1 Richard Henderson
2025-04-15 22:07 ` Pierrick Bouvier
2025-04-16 6:37 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 112/163] tcg: Sink def, nb_iargs, nb_oargs loads " Richard Henderson
2025-04-15 22:09 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 113/163] tcg: Add add/sub with carry opcodes and infrastructure Richard Henderson
2025-04-16 19:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 114/163] tcg: Add TCGOutOp structures for add/sub carry opcodes Richard Henderson
2025-04-16 18:56 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 115/163] tcg/optimize: Handle add/sub with " Richard Henderson
2025-04-16 19:02 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 116/163] tcg/optimize: With two const operands, prefer 0 in arg1 Richard Henderson
2025-04-16 19:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 117/163] tcg: Use add carry opcodes to expand add2 Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 118/163] tcg: Use sub carry opcodes to expand sub2 Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 119/163] tcg/i386: Honor carry_live in tcg_out_movi Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 120/163] tcg/i386: Implement add/sub carry opcodes Richard Henderson
2025-04-16 18:58 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 121/163] tcg/i386: Remove support for add2/sub2 Richard Henderson
2025-04-16 18:58 ` Pierrick Bouvier
2025-04-22 16:13 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 122/163] tcg/i386: Special case addci r, 0, 0 Richard Henderson
2025-04-16 18:59 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 123/163] tcg: Add tcg_gen_addcio_{i32,i64,tl} Richard Henderson
2025-04-16 18:59 ` Pierrick Bouvier
2025-04-22 16:13 ` Philippe Mathieu-Daudé
2025-04-22 16:30 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 124/163] target/arm: Use tcg_gen_addcio_* for ADCS Richard Henderson
2025-04-16 19:00 ` Pierrick Bouvier
2025-04-22 16:15 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 125/163] target/hppa: Use tcg_gen_addcio_i64 Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:17 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 126/163] target/microblaze: Use tcg_gen_addcio_i32 Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:28 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 127/163] target/openrisc: Use tcg_gen_addcio_* for ADDC Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:32 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 128/163] target/ppc: Use tcg_gen_addcio_tl for ADD and SUBF Richard Henderson
2025-04-16 14:08 ` Nicholas Piggin
2025-04-16 19:08 ` Pierrick Bouvier
2025-04-22 16:33 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 129/163] target/s390x: Use tcg_gen_addcio_i64 for op_addc64 Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:33 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 130/163] target/sh4: Use tcg_gen_addcio_i32 for addc Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:34 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 131/163] target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_int Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 132/163] target/tricore: Use tcg_gen_addcio_i32 for gen_addc_CC Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:38 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 133/163] tcg/aarch64: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:10 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 134/163] tcg/aarch64: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:13 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 135/163] tcg/arm: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 136/163] tcg/arm: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 137/163] tcg/ppc: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 138/163] tcg/ppc: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:15 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 139/163] tcg/s390x: Honor carry_live in tcg_out_movi Richard Henderson
2025-04-16 19:15 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 140/163] tcg/s390: Add TCG_CT_CONST_N32 Richard Henderson
2025-04-16 19:16 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 141/163] tcg/s390x: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:16 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 142/163] tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE Richard Henderson
2025-04-16 19:18 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 143/163] tcg/s390x: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:18 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 144/163] tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc Richard Henderson
2025-04-16 6:40 ` Philippe Mathieu-Daudé
2025-04-16 19:19 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 145/163] tcg/sparc64: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:20 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 146/163] tcg/sparc64: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:20 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 147/163] tcg/tci: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:36 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 148/163] tcg/tci: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:37 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 149/163] tcg: Remove add2/sub2 opcodes Richard Henderson
2025-04-16 19:37 ` Pierrick Bouvier
2025-04-22 16:42 ` Philippe Mathieu-Daudé
2025-04-22 17:10 ` Richard Henderson
2025-04-15 19:25 ` [PATCH v4 150/163] tcg: Formalize tcg_out_mb Richard Henderson
2025-04-16 19:38 ` Pierrick Bouvier
2025-04-22 16:44 ` Philippe Mathieu-Daudé
2025-04-15 19:25 ` [PATCH v4 151/163] tcg: Formalize tcg_out_br Richard Henderson
2025-04-16 19:38 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 152/163] tcg: Formalize tcg_out_goto_ptr Richard Henderson
2025-04-16 20:45 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 153/163] tcg: Assign TCGOP_TYPE in liveness_pass_2 Richard Henderson
2025-04-16 20:46 ` Pierrick Bouvier
2025-04-18 10:46 ` Nicholas Piggin
2025-04-21 16:28 ` Richard Henderson
2025-04-15 19:25 ` [PATCH v4 154/163] tcg: Convert ld to TCGOutOpLoad Richard Henderson
2025-04-16 20:52 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 155/163] tcg: Merge INDEX_op_ld*_{i32,i64} Richard Henderson
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 156/163] tcg: Convert st to TCGOutOpStore Richard Henderson
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 157/163] tcg: Merge INDEX_op_st*_{i32,i64} Richard Henderson
2025-04-16 7:05 ` Philippe Mathieu-Daudé
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 158/163] tcg: Stash MemOp size in TCGOP_FLAGS Richard Henderson
2025-04-16 6:55 ` Philippe Mathieu-Daudé
2025-04-16 20:54 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 159/163] tcg: Remove INDEX_op_qemu_st8_* Richard Henderson
2025-04-16 6:55 ` Philippe Mathieu-Daudé
2025-04-16 19:24 ` Richard Henderson
2025-04-16 20:55 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 160/163] tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128} Richard Henderson
2025-04-16 20:56 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 161/163] tcg: Convert qemu_ld{2} to TCGOutOpLoad{2} Richard Henderson
2025-04-16 20:57 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 162/163] tcg: Convert qemu_st{2} to TCGOutOpLdSt{2} Richard Henderson
2025-04-16 20:58 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 163/163] tcg: Remove tcg_out_op Richard Henderson
2025-04-16 19:04 ` Pierrick Bouvier
2025-04-16 13:24 ` [PATCH v4 000/163] tcg: Convert to TCGOutOp structures Nicholas Piggin
2025-04-16 23:38 ` Pierrick Bouvier
2025-04-17 0:18 ` Richard Henderson
2025-04-17 0:49 ` Pierrick Bouvier
2025-04-17 12:02 ` BALATON Zoltan
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