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[88.21.207.26]) by smtp.gmail.com with ESMTPSA id o18sm2347255wrp.23.2020.05.06.04.42.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 May 2020 04:42:55 -0700 (PDT) Subject: Re: [PATCH v2 4/9] hw/dma/xilinx_axidma: Add DMA memory-region property To: "Edgar E. Iglesias" , qemu-devel@nongnu.org References: <20200506082513.18751-1-edgar.iglesias@gmail.com> <20200506082513.18751-5-edgar.iglesias@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <6e5b9aa9-aff2-25b6-c294-4764d38e3bb8@amsat.org> Date: Wed, 6 May 2020 13:42:54 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20200506082513.18751-5-edgar.iglesias@gmail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: damien.hedde@greensocs.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, jasowang@redhat.com, alistair@alistair23.me, frederic.konrad@adacore.com, qemu-arm@nongnu.org, figlesia@xilinx.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Edgar, On 5/6/20 10:25 AM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Add DMA memory-region property to externally control what > address-space this DMA operates on. > > Reviewed-by: Alistair Francis > Reviewed-by: Francisco Iglesias > Signed-off-by: Edgar E. Iglesias > --- > hw/dma/xilinx_axidma.c | 30 +++++++++++++++++++++++------- > 1 file changed, 23 insertions(+), 7 deletions(-) > > diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c > index 018f36991b..4540051448 100644 > --- a/hw/dma/xilinx_axidma.c > +++ b/hw/dma/xilinx_axidma.c > @@ -33,6 +33,7 @@ > #include "qemu/log.h" > #include "qemu/module.h" > > +#include "sysemu/dma.h" > #include "hw/stream.h" > > #define D(x) > @@ -103,6 +104,7 @@ enum { > }; > > struct Stream { > + struct XilinxAXIDMA *dma; > ptimer_state *ptimer; > qemu_irq irq; > > @@ -125,6 +127,9 @@ struct XilinxAXIDMAStreamSlave { > struct XilinxAXIDMA { > SysBusDevice busdev; > MemoryRegion iomem; > + MemoryRegion *dma_mr; > + AddressSpace as; > + > uint32_t freqhz; > StreamSlave *tx_data_dev; > StreamSlave *tx_control_dev; > @@ -186,7 +191,7 @@ static void stream_desc_load(struct Stream *s, hwaddr addr) > { > struct SDesc *d = &s->desc; > > - cpu_physical_memory_read(addr, d, sizeof *d); > + address_space_read(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED, d, sizeof *d); > > /* Convert from LE into host endianness. */ > d->buffer_address = le64_to_cpu(d->buffer_address); > @@ -204,7 +209,8 @@ static void stream_desc_store(struct Stream *s, hwaddr addr) > d->nxtdesc = cpu_to_le64(d->nxtdesc); > d->control = cpu_to_le32(d->control); > d->status = cpu_to_le32(d->status); > - cpu_physical_memory_write(addr, d, sizeof *d); > + address_space_write(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED, > + d, sizeof *d); > } > > static void stream_update_irq(struct Stream *s) > @@ -286,8 +292,9 @@ static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev, > txlen + s->pos); > } > > - cpu_physical_memory_read(s->desc.buffer_address, > - s->txbuf + s->pos, txlen); > + address_space_read(&s->dma->as, s->desc.buffer_address, > + MEMTXATTRS_UNSPECIFIED, > + s->txbuf + s->pos, txlen); > s->pos += txlen; > > if (stream_desc_eof(&s->desc)) { > @@ -336,7 +343,8 @@ static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf, > rxlen = len; > } > > - cpu_physical_memory_write(s->desc.buffer_address, buf + pos, rxlen); > + address_space_write(&s->dma->as, s->desc.buffer_address, > + MEMTXATTRS_UNSPECIFIED, buf + pos, rxlen); > len -= rxlen; > pos += rxlen; > > @@ -525,6 +533,7 @@ static void xilinx_axidma_realize(DeviceState *dev, Error **errp) > XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM( > &s->rx_control_dev); > Error *local_err = NULL; > + int i; > > object_property_add_link(OBJECT(ds), "dma", TYPE_XILINX_AXI_DMA, > (Object **)&ds->dma, > @@ -545,17 +554,19 @@ static void xilinx_axidma_realize(DeviceState *dev, Error **errp) > goto xilinx_axidma_realize_fail; > } > > - int i; > - > for (i = 0; i < 2; i++) { > struct Stream *st = &s->streams[i]; > > + st->dma = s; > st->nr = i; > st->ptimer = ptimer_init(timer_hit, st, PTIMER_POLICY_DEFAULT); > ptimer_transaction_begin(st->ptimer); > ptimer_set_freq(st->ptimer, s->freqhz); > ptimer_transaction_commit(st->ptimer); > } > + > + address_space_init(&s->as, > + s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); I'd instead return an error (earlier in this function) if dma_mr property is not set. If you ever respin... Reviewed-by: Philippe Mathieu-Daudé > return; > > xilinx_axidma_realize_fail: > @@ -575,6 +586,11 @@ static void xilinx_axidma_init(Object *obj) > &s->rx_control_dev, sizeof(s->rx_control_dev), > TYPE_XILINX_AXI_DMA_CONTROL_STREAM, &error_abort, > NULL); > + object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, > + (Object **)&s->dma_mr, > + qdev_prop_allow_set_link_before_realize, > + OBJ_PROP_LINK_STRONG, > + &error_abort); > > sysbus_init_irq(sbd, &s->streams[0].irq); > sysbus_init_irq(sbd, &s->streams[1].irq); >